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Sat, 15 Sep 2018 01:34:35 +0000 Received: from CY4PR21MB0776.namprd21.prod.outlook.com ([fe80::151:b6fe:32c8:cccd]) by CY4PR21MB0776.namprd21.prod.outlook.com ([fe80::151:b6fe:32c8:cccd%9]) with mapi id 15.20.1164.008; Sat, 15 Sep 2018 01:34:35 +0000 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Thierry Reding , Ben Skeggs , Sasha Levin Subject: [PATCH AUTOSEL 4.9 16/34] drm/nouveau: tegra: Detach from ARM DMA/IOMMU mapping Thread-Topic: [PATCH AUTOSEL 4.9 16/34] drm/nouveau: tegra: Detach from ARM DMA/IOMMU mapping Thread-Index: AQHUTJRCUSrIrzYk9U6Mfjvm4+Ot6w== Date: Sat, 15 Sep 2018 01:34:35 +0000 Message-ID: <20180915013422.180023-16-alexander.levin@microsoft.com> References: <20180915013422.180023-1-alexander.levin@microsoft.com> In-Reply-To: <20180915013422.180023-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;CY4PR21MB0823;6:RhAOt1fGnVa1vrhKxq0xsuELpw1YUdaGLj+0QRlggNzPqLfxNafE7BXFcY1FMJCu5D9Xqoeu7m5D7aia3A32o38tND6/TmWQ3yo9tVf6IyJFKRQL453NYPYHGXaQtQ7djygThc953S8h3spkUyV5vjNwKn01E+JmB9dy2X8Hq5w6lLOGeiA2Dq903p8rvPvsKZh8RxWxl0nleMrPAZl4SEH+7yfNpSrLBZhj7eeolh3lMJAD2uM15GujrOP5Yl2uy0E0FbpA94NNDuf9gEK/IchsIdjy8tdO1itpOWTzdKbqVIPx3xF64WRX6E/e3h1OQoRL4le7+gN1R7H6unoR8GJrGcyaPmpn/whkLJMLx9n7WGLAwHhtjY+IBXsMjVlmWSXJBOJZQBsyLn5VWgM8du3y6pQ39FwUIKlvZJyRWG2Ta3PyoQLj9iPO4NYnzrsLemr8+xhLWrKA2RGlEOkqfQ==;5:79Fslji0gT2PSwa0xsB+CxXNX81gUSXOR71f3AZzodrMJn4w3CZSpWR9iKkraRSQE6FGNDDScSkl/U+p1yTsrw5WB+aJVLiuSZHspKwlD54fQmPb4aV2+D+upO6LIT4ppJRW5ibdVdBSpP3i+Vb3+66strRghGMatXskA8BEvz8=;7:WQCn37tHTHpDtQVcHpvuP6QbRtBj+U/8l+xa9rGN7w4N5jamSTCSJiHBX8pJCOue83ljbcFfqi9NILx9mziEA5ypY1BcHiJpnZyVNZhZBxJiGl3K88JdR5407JGGgd5pmgJJ600o3i9R2Sq5k4GD930zgMql4ZsnmijHMxyDwsuY4i2jkl0BEuVIWaCnYjuCY06GPHzHQb6LEXRMD6Z/l+cqYVgUYkX6cKEXNFipFqOYBk5+zxwhjXNgoe0QuCaX x-ms-office365-filtering-correlation-id: 45967de7-5147-4efe-aa89-08d61aab6508 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7193020);SRVR:CY4PR21MB0823; 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received-spf: None (protection.outlook.com: microsoft.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alexander.Levin@microsoft.com; x-microsoft-antispam-message-info: dnR/ZCXGvaKfcBF+1XixdkWj/x3S3ROuvrhq2CXjRTr0xuzSPgiyo7pmKD8DBd7aUVslD4IHq9csce3McKDqbShuMkQGkYu9YRRoi673dUl7+/H95vzXU4qtvtH1H2N35C55sPPH0GV3yBli45K+VPCeyskU2QvCMNxuYQUVlDgr6s2/D619dyXlqrezXvKsROznF0WgGl4mJl8Acqd0FZVNkwf4LhpfWOa4oRli9atXrTP/H/OVm3BL2Ku7krCp6+I7d1KNm+AECfdklXJyYOTXM9Em3UFmemD+oddXEmSEpPrw7xvUZf3BQFOflpMQ8gLaR5NTKgNpmjshu0p7WFRfTCZq4BvmEBgcsjDN0RU= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 45967de7-5147-4efe-aa89-08d61aab6508 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Sep 2018 01:34:35.5050 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR21MB0823 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thierry Reding [ Upstream commit b59fb482b52269977ee5de205308e5b236a03917 ] Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the memory controller). Transparently backing DMA memory with an IOMMU prevents Nouveau from properly handling such memory accesses and causes memory access faults. As a side-note: buffers other than those allocated in instance memory don't need to be physically contiguous from the GPU's perspective since the GPU can map them into contiguous buffers using its own MMU. Mapping these buffers through the IOMMU is unnecessary and will even lead to performance degradation because of the additional translation. One exception to this are compressible buffers which need large pages. In order to enable these large pages, multiple small pages will have to be combined into one large (I/O virtually contiguous) mapping via the IOMMU. However, that is a topic outside the scope of this fix and isn't currently supported. An implementation will want to explicitly create these large pages in the Nouveau driver, so detaching from a DMA/IOMMU mapping would still be required. Signed-off-by: Thierry Reding Acked-by: Christoph Hellwig Reviewed-by: Robin Murphy Tested-by: Nicolas Chauvet Signed-off-by: Ben Skeggs Signed-off-by: Sasha Levin --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/g= pu/drm/nouveau/nvkm/engine/device/tegra.c index 9b638bd905ff..d370bf8bc409 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c @@ -23,6 +23,10 @@ #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER #include "priv.h" =20 +#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) +#include +#endif + static int nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev) { @@ -95,6 +99,15 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *= tdev) unsigned long pgsize_bitmap; int ret; =20 +#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) + if (dev->archdata.mapping) { + struct dma_iommu_mapping *mapping =3D to_dma_iommu_mapping(dev); + + arm_iommu_detach_device(dev); + arm_iommu_release_mapping(mapping); + } +#endif + if (!tdev->func->iommu_bit) return; =20 --=20 2.17.1