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Mon, 24 Sep 2018 19:18:54 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::5c18:7df5:fd4b:9de]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::5c18:7df5:fd4b:9de%5]) with mapi id 15.20.1164.024; Mon, 24 Sep 2018 19:18:54 +0000 From: "Moger, Babu" To: "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "fenghua.yu@intel.com" , "reinette.chatre@intel.com" , "vikas.shivappa@linux.intel.com" , "tony.luck@intel.com" CC: "x86@kernel.org" , "peterz@infradead.org" , "Moger, Babu" , "pombredanne@nexb.com" , "gregkh@linuxfoundation.org" , "kstewart@linuxfoundation.org" , "bp@suse.de" , "rafael.j.wysocki@intel.com" , "ak@linux.intel.com" , "kirill.shutemov@linux.intel.com" , "xiaochen.shen@intel.com" , "colin.king@canonical.com" , "Hurwitz, Sherry" , "Lendacky, Thomas" , "pbonzini@redhat.com" , "dwmw@amazon.co.uk" , "luto@kernel.org" , "jroedel@suse.de" , "jannh@google.com" , "dima@arista.com" , "jpoimboe@redhat.com" , "vkuznets@redhat.com" , "linux-kernel@vger.kernel.org" Subject: [RFC PATCH 00/10] arch/x86: AMD QoS support Thread-Topic: [RFC PATCH 00/10] arch/x86: AMD QoS support Thread-Index: AQHUVDtunpE+5D/HD063flof44uaLQ== Date: Mon, 24 Sep 2018 19:18:54 +0000 Message-ID: <20180924191841.29111-1-babu.moger@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR15CA0009.namprd15.prod.outlook.com (2603:10b6:805:16::22) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 475418c7-3439-48a9-d263-08d622529110 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Sep 2018 19:18:54.2559 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2455 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series adds support for AMD64 architectural extensions for Platform Quality of Service. These extensions are intended to provide for the monitoring of the usage of certain system resources by one or more processors and for the separate allocation and enforcement of limits on the use of certain system resources by one or more processors. The monitoring and enforcement are not necessarily applied across the entire system, but in general apply to a QOS domain which corresponds to some shared system resource. The set of resources which are monitored and the set for which the enforcement of limits is provided are implementation dependent. Platform QOS features are implemented on a logical processor bas= is. Therefore, multiple hardware threads of a single physical CPU core may have independent resource monitoring and enforcement configurations. AMD's next generation of processors support following QoS sub-features. - L3 Cache allocation enforcement - L3 Cache occupancy monitoring - L3 Code-Data Prioritization support - Memory Bandwidth Enforcement(Allocation) The public specification is still in works. Will add the link when it is available. Obviously, there are multiple ways we can go about these changes. We felt it is appropriate to rename and re-organize the code little bit before making the functional changes. The first few patches(1-6) renames and re-organizes the sources in preparation. Rest of the patches(7-10) adds support for AMD QoS features. Please review and provide me feedback. If you think of better way to approach this, please let us know.=20 Babu Moger (9): arch/x86: Start renaming the rdt files to more generic names arch/x86: Rename the RDT functions and definitions arch/x86: Re-arrange RDT init code arch/x86: Introduce a new config parameter PLATFORM_QOS arch/x86: Use new config parameter PLATFORM_QOS for compilation arch/x86: Initialize the resource functions that are different arch/x86: Bring few more functions into the resource structure arch/x86: Introduce new config parameter AMD_QOS arch/x86: Introduce QOS feature for AMD Sherry Hurwitz (1): arch/x86: Add AMD feature bit X86_FEATURE_MBA in cpuid bits array arch/x86/Kconfig | 19 ++ .../asm/{intel_rdt_sched.h =3D> rdt_sched.h} | 26 +-- arch/x86/kernel/cpu/Makefile | 6 +- arch/x86/kernel/cpu/{intel_rdt.c =3D> rdt.c} | 175 +++++++++++++++--- arch/x86/kernel/cpu/{intel_rdt.h =3D> rdt.h} | 34 +++- ...el_rdt_ctrlmondata.c =3D> rdt_ctrlmondata.c} | 87 ++++++++- .../{intel_rdt_monitor.c =3D> rdt_monitor.c} | 22 ++- ...el_rdt_pseudo_lock.c =3D> rdt_pseudo_lock.c} | 6 +- ...o_lock_event.h =3D> rdt_pseudo_lock_event.h} | 2 +- .../{intel_rdt_rdtgroup.c =3D> rdt_rdtgroup.c} | 14 +- arch/x86/kernel/cpu/scattered.c | 1 + arch/x86/kernel/process_32.c | 4 +- arch/x86/kernel/process_64.c | 4 +- include/linux/sched.h | 2 +- 14 files changed, 319 insertions(+), 83 deletions(-) rename arch/x86/include/asm/{intel_rdt_sched.h =3D> rdt_sched.h} (80%) rename arch/x86/kernel/cpu/{intel_rdt.c =3D> rdt.c} (84%) rename arch/x86/kernel/cpu/{intel_rdt.h =3D> rdt.h} (93%) rename arch/x86/kernel/cpu/{intel_rdt_ctrlmondata.c =3D> rdt_ctrlmondata.c= } (84%) rename arch/x86/kernel/cpu/{intel_rdt_monitor.c =3D> rdt_monitor.c} (97%) rename arch/x86/kernel/cpu/{intel_rdt_pseudo_lock.c =3D> rdt_pseudo_lock.c= } (99%) rename arch/x86/kernel/cpu/{intel_rdt_pseudo_lock_event.h =3D> rdt_pseudo_= lock_event.h} (95%) rename arch/x86/kernel/cpu/{intel_rdt_rdtgroup.c =3D> rdt_rdtgroup.c} (99%= ) --=20 2.17.1