Re: [PATCH V5 06/30] csky: Cache and TLB routines

Peter Zijlstra
2018-09-27T09:02:06Z

On Thu, Sep 27, 2018 at 04:11:42PM +0800, Guo Ren wrote:
> On Thu, Sep 27, 2018 at 09:08:59AM +0200, Peter Zijlstra wrote:

> > That's not what I meant; I meant you need something like:
> >
> > #define flush_cache_range(vma, start, end) cache_wbinv_range(start, end)
> If you remove the tlb_start_vma in my tlb.h, I want to use cache_wbinv_all() is
> more safe. And I'll improve it in future.
>
> My cache_wbinv_range(start, end) won't care vma->mm's asid and they just use current
> asid in mmu reg. If current_mm != vma->mm, then flush_cache_range will be broken.
> Perhaps, I need improve flush_cache_range first ...

Ah, ok. In that case I'll leave it to you to either use
cache_wbinv_all() or improve the range flush. My only request would to
stick on a comment to explain the reason you're not using
cache_wbinv_range() if you choose to use cache_wbinv_all() for
flush_cache_range().

Thanks!