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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 044f2e7a-80df-4541-e6b2-08d64c05b0c8 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2018 20:54:24.6619 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1788 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As AMD is starting to support RDT(or QOS) features, rename the RDT functions and definitions to more generic names. Replace intel_rdt to resctrl where applicable. Signed-off-by: Babu Moger Reviewed-by: Borislav Petkov --- arch/x86/include/asm/resctrl_sched.h | 24 ++++++++++++------------ arch/x86/kernel/cpu/resctrl.c | 26 +++++++++++++------------- arch/x86/kernel/cpu/resctrl.h | 2 +- arch/x86/kernel/cpu/resctrl_monitor.c | 11 ++++++----- arch/x86/kernel/cpu/resctrl_rdtgroup.c | 10 +++++----- arch/x86/kernel/process_32.c | 2 +- arch/x86/kernel/process_64.c | 2 +- 7 files changed, 39 insertions(+), 38 deletions(-) diff --git a/arch/x86/include/asm/resctrl_sched.h b/arch/x86/include/asm/re= sctrl_sched.h index 9acb06b6f81e..6e082697a613 100644 --- a/arch/x86/include/asm/resctrl_sched.h +++ b/arch/x86/include/asm/resctrl_sched.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_X86_INTEL_RDT_SCHED_H -#define _ASM_X86_INTEL_RDT_SCHED_H +#ifndef _ASM_X86_RESCTRL_SCHED_H +#define _ASM_X86_RESCTRL_SCHED_H =20 #ifdef CONFIG_INTEL_RDT =20 @@ -10,7 +10,7 @@ #define IA32_PQR_ASSOC 0x0c8f =20 /** - * struct intel_pqr_state - State cache for the PQR MSR + * struct resctrl_pqr_state - State cache for the PQR MSR * @cur_rmid: The cached Resource Monitoring ID * @cur_closid: The cached Class Of Service ID * @default_rmid: The user assigned Resource Monitoring ID @@ -24,21 +24,21 @@ * The cache also helps to avoid pointless updates if the value does * not change. */ -struct intel_pqr_state { +struct resctrl_pqr_state { u32 cur_rmid; u32 cur_closid; u32 default_rmid; u32 default_closid; }; =20 -DECLARE_PER_CPU(struct intel_pqr_state, pqr_state); +DECLARE_PER_CPU(struct resctrl_pqr_state, pqr_state); =20 DECLARE_STATIC_KEY_FALSE(rdt_enable_key); DECLARE_STATIC_KEY_FALSE(rdt_alloc_enable_key); DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); =20 /* - * __intel_rdt_sched_in() - Writes the task's CLOSid/RMID to IA32_PQR_MSR + * __resctrl_sched_in() - Writes the task's CLOSid/RMID to IA32_PQR_MSR * * Following considerations are made so that this has minimal impact * on scheduler hot path: @@ -51,9 +51,9 @@ DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); * simple as possible. * Must be called with preemption disabled. */ -static void __intel_rdt_sched_in(void) +static void __resctrl_sched_in(void) { - struct intel_pqr_state *state =3D this_cpu_ptr(&pqr_state); + struct resctrl_pqr_state *state =3D this_cpu_ptr(&pqr_state); u32 closid =3D state->default_closid; u32 rmid =3D state->default_rmid; =20 @@ -78,16 +78,16 @@ static void __intel_rdt_sched_in(void) } } =20 -static inline void intel_rdt_sched_in(void) +static inline void resctrl_sched_in(void) { if (static_branch_likely(&rdt_enable_key)) - __intel_rdt_sched_in(); + __resctrl_sched_in(); } =20 #else =20 -static inline void intel_rdt_sched_in(void) {} +static inline void resctrl_sched_in(void) {} =20 #endif /* CONFIG_INTEL_RDT */ =20 -#endif /* _ASM_X86_INTEL_RDT_SCHED_H */ +#endif /* _ASM_X86_RESCTRL_SCHED_H */ diff --git a/arch/x86/kernel/cpu/resctrl.c b/arch/x86/kernel/cpu/resctrl.c index 3f1a135a4ae0..5d526dc45751 100644 --- a/arch/x86/kernel/cpu/resctrl.c +++ b/arch/x86/kernel/cpu/resctrl.c @@ -40,12 +40,12 @@ DEFINE_MUTEX(rdtgroup_mutex); =20 /* - * The cached intel_pqr_state is strictly per CPU and can never be + * The cached resctrl_pqr_state is strictly per CPU and can never be * updated from a remote CPU. Functions which modify the state * are called with interrupts disabled and no preemption, which * is sufficient for the protection. */ -DEFINE_PER_CPU(struct intel_pqr_state, pqr_state); +DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); =20 /* * Used to store the max resource name width and max resource data width @@ -639,7 +639,7 @@ static void domain_remove_cpu(int cpu, struct rdt_resou= rce *r) =20 static void clear_closid_rmid(int cpu) { - struct intel_pqr_state *state =3D this_cpu_ptr(&pqr_state); + struct resctrl_pqr_state *state =3D this_cpu_ptr(&pqr_state); =20 state->default_closid =3D 0; state->default_rmid =3D 0; @@ -648,7 +648,7 @@ static void clear_closid_rmid(int cpu) wrmsr(IA32_PQR_ASSOC, 0, 0); } =20 -static int intel_rdt_online_cpu(unsigned int cpu) +static int resctrl_online_cpu(unsigned int cpu) { struct rdt_resource *r; =20 @@ -674,7 +674,7 @@ static void clear_childcpus(struct rdtgroup *r, unsigne= d int cpu) } } =20 -static int intel_rdt_offline_cpu(unsigned int cpu) +static int resctrl_offline_cpu(unsigned int cpu) { struct rdtgroup *rdtgrp; struct rdt_resource *r; @@ -866,7 +866,7 @@ static __init bool get_rdt_resources(void) =20 static enum cpuhp_state rdt_online; =20 -static int __init intel_rdt_late_init(void) +static int __init resctrl_late_init(void) { struct rdt_resource *r; int state, ret; @@ -877,8 +877,8 @@ static int __init intel_rdt_late_init(void) rdt_init_padding(); =20 state =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, - "x86/rdt/cat:online:", - intel_rdt_online_cpu, intel_rdt_offline_cpu); + "x86/resctrl/cat:online:", + resctrl_online_cpu, resctrl_offline_cpu); if (state < 0) return state; =20 @@ -890,20 +890,20 @@ static int __init intel_rdt_late_init(void) rdt_online =3D state; =20 for_each_alloc_capable_rdt_resource(r) - pr_info("Intel RDT %s allocation detected\n", r->name); + pr_info("%s allocation detected\n", r->name); =20 for_each_mon_capable_rdt_resource(r) - pr_info("Intel RDT %s monitoring detected\n", r->name); + pr_info("%s monitoring detected\n", r->name); =20 return 0; } =20 -late_initcall(intel_rdt_late_init); +late_initcall(resctrl_late_init); =20 -static void __exit intel_rdt_exit(void) +static void __exit resctrl_exit(void) { cpuhp_remove_state(rdt_online); rdtgroup_exit(); } =20 -__exitcall(intel_rdt_exit); +__exitcall(resctrl_exit); diff --git a/arch/x86/kernel/cpu/resctrl.h b/arch/x86/kernel/cpu/resctrl.h index a9d906767bb2..abf5c7e4c625 100644 --- a/arch/x86/kernel/cpu/resctrl.h +++ b/arch/x86/kernel/cpu/resctrl.h @@ -69,7 +69,7 @@ struct rmid_read { u64 val; }; =20 -extern unsigned int intel_cqm_threshold; +extern unsigned int resctrl_cqm_threshold; extern bool rdt_alloc_capable; extern bool rdt_mon_capable; extern unsigned int rdt_mon_features; diff --git a/arch/x86/kernel/cpu/resctrl_monitor.c b/arch/x86/kernel/cpu/re= sctrl_monitor.c index 211d97bcbde5..6d654f7b0eba 100644 --- a/arch/x86/kernel/cpu/resctrl_monitor.c +++ b/arch/x86/kernel/cpu/resctrl_monitor.c @@ -73,7 +73,7 @@ unsigned int rdt_mon_features; * This is the threshold cache occupancy at which we will consider an * RMID available for re-allocation. */ -unsigned int intel_cqm_threshold; +unsigned int resctrl_cqm_threshold; =20 static inline struct rmid_entry *__rmid_entry(u32 rmid) { @@ -107,7 +107,7 @@ static bool rmid_dirty(struct rmid_entry *entry) { u64 val =3D __rmid_read(entry->rmid, QOS_L3_OCCUP_EVENT_ID); =20 - return val >=3D intel_cqm_threshold; + return val >=3D resctrl_cqm_threshold; } =20 /* @@ -187,7 +187,7 @@ static void add_rmid_to_limbo(struct rmid_entry *entry) list_for_each_entry(d, &r->domains, list) { if (cpumask_test_cpu(cpu, &d->cpu_mask)) { val =3D __rmid_read(entry->rmid, QOS_L3_OCCUP_EVENT_ID); - if (val <=3D intel_cqm_threshold) + if (val <=3D resctrl_cqm_threshold) continue; } =20 @@ -625,6 +625,7 @@ static void l3_mon_evt_init(struct rdt_resource *r) =20 int rdt_get_mon_l3_config(struct rdt_resource *r) { + unsigned int cl_size =3D boot_cpu_data.x86_cache_size; int ret; =20 r->mon_scale =3D boot_cpu_data.x86_cache_occ_scale; @@ -637,10 +638,10 @@ int rdt_get_mon_l3_config(struct rdt_resource *r) * * For a 35MB LLC and 56 RMIDs, this is ~1.8% of the LLC. */ - intel_cqm_threshold =3D boot_cpu_data.x86_cache_size * 1024 / r->num_rmid= ; + resctrl_cqm_threshold =3D cl_size * 1024 / r->num_rmid; =20 /* h/w works in units of "boot_cpu_data.x86_cache_occ_scale" */ - intel_cqm_threshold /=3D r->mon_scale; + resctrl_cqm_threshold /=3D r->mon_scale; =20 ret =3D dom_data_init(r); if (ret) diff --git a/arch/x86/kernel/cpu/resctrl_rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl_rdtgroup.c index 6308ba3905e5..8b6b4a8bb7ca 100644 --- a/arch/x86/kernel/cpu/resctrl_rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl_rdtgroup.c @@ -298,7 +298,7 @@ static int rdtgroup_cpus_show(struct kernfs_open_file *= of, } =20 /* - * This is safe against intel_rdt_sched_in() called from __switch_to() + * This is safe against resctrl_sched_in() called from __switch_to() * because __switch_to() is executed with interrupts disabled. A local cal= l * from update_closid_rmid() is proteced against __switch_to() because * preemption is disabled. @@ -317,7 +317,7 @@ static void update_cpu_closid_rmid(void *info) * executing task might have its own closid selected. Just reuse * the context switch code. */ - intel_rdt_sched_in(); + resctrl_sched_in(); } =20 /* @@ -542,7 +542,7 @@ static void move_myself(struct callback_head *head) =20 preempt_disable(); /* update PQR_ASSOC MSR to make resource group go into effect */ - intel_rdt_sched_in(); + resctrl_sched_in(); preempt_enable(); =20 kfree(callback); @@ -926,7 +926,7 @@ static int max_threshold_occ_show(struct kernfs_open_fi= le *of, { struct rdt_resource *r =3D of->kn->parent->priv; =20 - seq_printf(seq, "%u\n", intel_cqm_threshold * r->mon_scale); + seq_printf(seq, "%u\n", resctrl_cqm_threshold * r->mon_scale); =20 return 0; } @@ -945,7 +945,7 @@ static ssize_t max_threshold_occ_write(struct kernfs_op= en_file *of, if (bytes > (boot_cpu_data.x86_cache_size * 1024)) return -EINVAL; =20 - intel_cqm_threshold =3D bytes / r->mon_scale; + resctrl_cqm_threshold =3D bytes / r->mon_scale; =20 return nbytes; } diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index d16207e7d1e5..dc4d92764d1a 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -302,7 +302,7 @@ __switch_to(struct task_struct *prev_p, struct task_str= uct *next_p) this_cpu_write(current_task, next_p); =20 /* Load the Intel cache allocation PQR MSR. */ - intel_rdt_sched_in(); + resctrl_sched_in(); =20 return prev_p; } diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index af73223ad6ba..5ada7354b5d4 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -536,7 +536,7 @@ __switch_to(struct task_struct *prev_p, struct task_str= uct *next_p) } =20 /* Load the Intel cache allocation PQR MSR. */ - intel_rdt_sched_in(); + resctrl_sched_in(); =20 return prev_p; } --=20 2.17.1