Re: omap5 fixing palmas IRQ_TYPE_NONE warning leads to gpadc timeouts

[Thierry Reding <treding@nvidia.com>]

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On Fri, Nov 23, 2018 at 08:48:27AM -0800, Tony Lindgren wrote:
> * Jon Hunter <jonathanh@nvidia.com> [181120 11:14]:
> > On 19/11/2018 17:14, Tony Lindgren wrote:
> > > Well so commit 7e9d474954f4 ("ARM: tegra: Correct polarity for
> > > Tegra114 PMIC interrupt") states that tegra114 inverts the
> > > polarity of the PMIC interrupt. So adding Jon and Thierry to Cc.
> > 
> > Yes Tegra can invert the polarity of the PMIC interrupt.
> 
> So is there some IP on Tegra called "Tegra PMC" that is
> inverting the interrupt? Or is the "Tegra PMC" that commit
> 7e9d474954f4 mentions just the palmas configuration for
> inverting the interrupt?

Yes, there's indeed an IP called PMC (Power-Management Controller) on
Tegra. It has a special input that is usually wired up to the PMIC
interrupt and a bit in the control register that configures the polarity
of that interrupt. If the PMIC generates a low-active interrupt we
usually set that bit to make sure it is properly sampled by the PMC.

The symptoms of this being incorrectly configured is usually an
interrupt storm on the PMIC interrupt, which I think typically results
in the system not booting at all, or taking a very long time to boot
because of that storm.

> The problem I'm having is With omap5 where I can only get the
> PMIC interrupts working with IRQ_TYPE_LEVEL_HIGH if
> PALMAS_POLARITY_CTRL_INT_POLARITY is not set unlike for
> Tegra.

Does somebody have access to the Palmas documentation? That should
pretty clearly state what the default polarity is and what it changes to
if you set the interrupt polarity bit.

From what you're saying it sounds like either the logic is the wrong way
around in the Palmas MFD driver (and we correct it by switching it back
to the correct polarity in the PMC) or that you'd need to find some way
of inverting in on OMAP5.

Thierry

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