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[217.229.16.64]) by smtp.gmail.com with ESMTPSA id s27-v6sm109706ejm.14.2018.11.26.05.34.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Nov 2018 05:34:43 -0800 (PST) Date: Mon, 26 Nov 2018 14:34:41 +0100 From: Thierry Reding To: Lothar =?utf-8?Q?Wa=C3=9Fmann?= Cc: =?utf-8?B?Vm9rw6HEjQ==?= Michal , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Mark Rutland , "devicetree@vger.kernel.org" , "linux-pwm@vger.kernel.org" , Lukasz Majewski , "linux-kernel@vger.kernel.org" , Rob Herring , "kernel@pengutronix.de" , Fabio Estevam , Linus Walleij , viresh kumar Subject: Re: [RCF PATCH,v2,2/2] pwm: imx: Configure output to GPIO in disabled state Message-ID: <20181126133441.GA19710@ulmo> References: <20181115203733.qvonika6yhn2bsnb@pengutronix.de> <20181116083430.7f1d8452@ipc1.ka-ro> <20181116082557.l2ljgu3hsu7tvdci@pengutronix.de> <91640f9b-d219-553e-043a-c6151f2f68d7@ysoft.com> <20181122162359.ufngpgxkenlmgqni@pengutronix.de> <20181122190321.ktqegs7kpvhcemvi@pengutronix.de> <9da8c6d9-d97c-200c-d8e4-2eb9f73eedc5@ysoft.com> <20181126115123.GA15164@ulmo> <20181126132316.541a4131@ipc1.ka-ro> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="FCuugMFkClbJLl1L" Content-Disposition: inline In-Reply-To: <20181126132316.541a4131@ipc1.ka-ro> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --FCuugMFkClbJLl1L Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Nov 26, 2018 at 01:23:16PM +0100, Lothar Wa=C3=9Fmann wrote: > Thierry Reding wrote: >=20 > > On Fri, Nov 23, 2018 at 03:15:11PM +0000, Vok=C3=A1=C4=8D Michal wrote: > > > On 22.11.2018 20:03, Uwe Kleine-K=C3=B6nig wrote: =20 > > > > On Thu, Nov 22, 2018 at 04:46:39PM +0000, Vok=C3=A1=C4=8D Michal wr= ote: =20 > > > >> On 22.11.2018 17:23, Uwe Kleine-K=C3=B6nig wrote: =20 > > > >>> On Thu, Nov 22, 2018 at 03:42:14PM +0000, Vok=C3=A1=C4=8D Michal = wrote: =20 > > > >>>> On 16.11.2018 09:25, Uwe Kleine-K=C3=B6nig wrote: =20 > > > >>>>> On Fri, Nov 16, 2018 at 08:34:30AM +0100, Lothar Wa=C3=9Fmann w= rote: =20 > > > >>>>>> No. You can disable the output driver via pinctrl, so that onl= y the > > > >>>>>> selected pull-up/down is relevant. The pin function and GPIO r= egister > > > >>>>>> settings don't matter at all in this case. =20 > > > >>>> > > > >>>> Lothar, please can you be more specific how would you do that? I= FAIK the > > > >>>> pull-up/down internal resistors have effect only if the pin is c= onfigured > > > >>>> as GPIO *input* (on i.MX6 at least). See the TRM, 29.4.2.2 Outpu= t driver: > > > >>>> > > > >>>> "Internal pull-up, pull-down resistors, and pad keeper are d= isabled in > > > >>>> output mode." =20 > > > >=20 > > > > This would mean you'd have to rely on an external pull up for your = use > > > > case. I wouldn't be surprised however if DSE=3D0 wouldn't count as = "output > > > > mode". Given the reliability of NXP documentation I wouldn't bet ne= ither > > > > on one nor the other possibility. =20 > > >=20 > > > Yeah, the NXP documentation sometimes does not really match reality. > > > My use case is based on the fact that I configure the pin as input in > > > the driver. Then it works just fine. > > > =20 > > > >>> So I'd expect this to really work on i.MX6 but not the earlier So= Cs > > > >>> without a gpio specifier. =20 > > > >> > > > >> Maybe you would expect it to work but I already tested and measured > > > >> that weeks ago ;) It did not work. =20 > > > >=20 > > > > Which pin/gpio do we talk about? Which i.MX6 variant did you test t= his > > > > on? (Assuming i.MX6D or i.MX6Q and PAD_DISP0_DATA09, did you try se= tting > > > >=20 > > > > IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 (0x020E0194) =3D 0x00000005 > > > > IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 (0x020E04A8) =3D 0x0000b080 > > > >=20 > > > > and then play with GPIO 4.30 direction and output value?) =20 > > >=20 > > > My test setup is as follows: > > > - SoC is i.MX6DL or i.MX6S - I have three board variants in total. > > > - Pin used for PWM/GPIO is PAD_GPIO9. > > > - The pin is not connected to any circuit. Just a test point. > > > - pinctrl setup in DT: > > > - for "pwm": > > > - fsl,pins =3D > > > - IOMUXC_SW_MUX_CTL_PAD_GPIO09 =3D 0x00000004 > > > - IOMUXC_SW_PAD_CTL_PAD_GPIO09 =3D 0x00000008 > > >=20 > > > - for "gpio": > > > - fsl,pins =3D > > > - IOMUXC_SW_MUX_CTL_PAD_GPIO09 =3D 0x00000005 > > > - IOMUXC_SW_PAD_CTL_PAD_GPIO09 =3D 0x0000b000 =20 > >=20 > > Does it help if you additionally set the ODE bit (bit 11) here? > >=20 > That only helps to NOT actively pulling the pin HIGH, but the opposite > is what is needed here. =46rom the description in the reference manual it sounded like the ODE would avoid the pin from actively being driven anywhere if configured as output. So I was hoping that in conjunction with the pull-up it would actually do the right thing. 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