From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BE94C43441 for ; Tue, 27 Nov 2018 19:31:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B55E420645 for ; Tue, 27 Nov 2018 19:31:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B55E420645 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726441AbeK1GaC (ORCPT ); Wed, 28 Nov 2018 01:30:02 -0500 Received: from foss.arm.com ([217.140.101.70]:46464 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725764AbeK1GaB (ORCPT ); Wed, 28 Nov 2018 01:30:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 070703698; Tue, 27 Nov 2018 11:31:06 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CBC623F575; Tue, 27 Nov 2018 11:31:05 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id AB7191AE0A0D; Tue, 27 Nov 2018 19:31:23 +0000 (GMT) Date: Tue, 27 Nov 2018 19:31:23 +0000 From: Will Deacon To: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, vladimir.murzin@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com, Andre Przywara Subject: Re: [PATCH 1/7] arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE Message-ID: <20181127193123.GH5641@arm.com> References: <1541418917-14219-1-git-send-email-suzuki.poulose@arm.com> <1541418917-14219-2-git-send-email-suzuki.poulose@arm.com> <20181126140603.GA29684@arm.com> <20181126150956.GA24096@en101> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181126150956.GA24096@en101> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 26, 2018 at 03:09:56PM +0000, Suzuki K Poulose wrote: > On Mon, Nov 26, 2018 at 02:06:04PM +0000, Will Deacon wrote: > > On Mon, Nov 05, 2018 at 11:55:11AM +0000, Suzuki K Poulose wrote: > > > We have two entries for ARM64_WORKAROUND_CLEAN_CACHE capability : > > > > > > 1) ARM Errata 826319, 827319, 824069, 819472 on A53 r0p[012] > > > 2) ARM Errata 819472 on A53 r0p[01] > > > > > > Both have the same work around. Merge these entries to avoid > > > duplicate entries for a single capability. > > > > > > Cc: Will Deacon > > > Cc: Andre Przywara > > > Cc: Mark Rutland > > > Signed-off-by: Suzuki K Poulose > > > --- > > > arch/arm64/kernel/cpu_errata.c | 19 +++++++------------ > > > 1 file changed, 7 insertions(+), 12 deletions(-) > > > > > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > > > index a509e351..c825bc0 100644 > > > --- a/arch/arm64/kernel/cpu_errata.c > > > +++ b/arch/arm64/kernel/cpu_errata.c > > > @@ -573,24 +573,19 @@ static const struct midr_range arm64_harden_el2_vectors[] = { > > > const struct arm64_cpu_capabilities arm64_errata[] = { > > > #if defined(CONFIG_ARM64_ERRATUM_826319) || \ > > > defined(CONFIG_ARM64_ERRATUM_827319) || \ > > > - defined(CONFIG_ARM64_ERRATUM_824069) > > > + defined(CONFIG_ARM64_ERRATUM_824069) || \ > > > + defined(CONFIG_ARM64_ERRATUM_819472) > > > { > > > - /* Cortex-A53 r0p[012] */ > > > - .desc = "ARM errata 826319, 827319, 824069", > > > + /* > > > + * Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 > > > + * Cortex-A53 r0p[01] : ARM errata 819472 > > > + */ > > > + .desc = "ARM errata 826319, 827319, 824069, 819472", > > > .capability = ARM64_WORKAROUND_CLEAN_CACHE, > > > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), > > > .cpu_enable = cpu_enable_cache_maint_trap, > > > > Isn't this a semantic change wrt the Kconfig options? After this change, > > if I /only/ set CONFIG_ARM64_ERRATUM_819472=y, then I still get the > > workaround applied for CPUs > r0[p01] which isn't what I asked for. > > You're right. I could change this to : Indeed, and you'll probably need something similar for the other entries that you're merging. Will