From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8FADC04EB9 for ; Mon, 3 Dec 2018 17:33:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BFD0620850 for ; Mon, 3 Dec 2018 17:33:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BFD0620850 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726794AbeLCRdY (ORCPT ); Mon, 3 Dec 2018 12:33:24 -0500 Received: from foss.arm.com ([217.140.101.70]:43008 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725897AbeLCRdY (ORCPT ); Mon, 3 Dec 2018 12:33:24 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D96311682; Mon, 3 Dec 2018 09:33:17 -0800 (PST) Received: from e107155-lin (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 56F5D3F59C; Mon, 3 Dec 2018 09:33:09 -0800 (PST) Date: Mon, 3 Dec 2018 17:33:06 +0000 From: Sudeep Holla To: Atish Patra Cc: "linux-kernel@vger.kernel.org" , Albert Ou , Anup Patel , Ard Biesheuvel , Catalin Marinas , "devicetree@vger.kernel.org" , Dmitriy Cherkasov , Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , Juri Lelli , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , "linux-riscv@lists.infradead.org" , Mark Rutland , Morten Rasmussen , Palmer Dabbelt , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Thomas Gleixner , Will Deacon Subject: Re: [RFT PATCH v1 2/4] dt-binding: cpu-topology: Move cpu-map to a common binding. Message-ID: <20181203173306.GF17883@e107155-lin> References: <1543534100-3654-1-git-send-email-atish.patra@wdc.com> <1543534100-3654-3-git-send-email-atish.patra@wdc.com> <20181203165521.GB17883@e107155-lin> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 03, 2018 at 09:23:42AM -0800, Atish Patra wrote: > On 12/3/18 8:55 AM, Sudeep Holla wrote: > > On Thu, Nov 29, 2018 at 03:28:18PM -0800, Atish Patra wrote: > > > cpu-map binding can be used to described cpu topology for both > > > RISC-V & ARM. It makes more sense to move the binding to document > > > to a common place. > > > > > > The relevant discussion can be found here. > > > https://lkml.org/lkml/2018/11/6/19 > > > > > > > Looks good to me apart from a minor query below in the example. > > > > Reviewed-by: Sudeep Holla > > > > > Signed-off-by: Atish Patra > > > --- > > > .../{arm/topology.txt => cpu/cpu-topology.txt} | 81 ++++++++++++++++++---- > > > 1 file changed, 67 insertions(+), 14 deletions(-) > > > rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (86%) > > > > > > diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt > > > similarity index 86% > > > rename from Documentation/devicetree/bindings/arm/topology.txt > > > rename to Documentation/devicetree/bindings/cpu/cpu-topology.txt > > > index 66848355..1de6fbce 100644 > > > --- a/Documentation/devicetree/bindings/arm/topology.txt > > > +++ b/Documentation/devicetree/bindings/cpu/cpu-topology.txt > > > > [...] > > > > > +Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) > > > + > > > +cpus { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + compatible = "sifive,fu540g", "sifive,fu500"; > > > + model = "sifive,hifive-unleashed-a00"; > > > + > > > + ... > > > + > > > + cpu-map { > > > + cluster0 { > > > + core0 { > > > + cpu = <&L12>; > > > + }; > > > + core1 { > > > + cpu = <&L15>; > > > + }; > > > + core2 { > > > + cpu0 = <&L18>; > > > + }; > > > + core3 { > > > + cpu0 = <&L21>; > > > + }; > > > + }; > > > + }; > > > + > > > + L12: cpu@1 { > > > + device_type = "cpu"; > > > + compatible = "sifive,rocket0", "riscv"; > > > + reg = <0x1>; > > > + } > > > + > > > + L15: cpu@2 { > > > + device_type = "cpu"; > > > + compatible = "sifive,rocket0", "riscv"; > > > + reg = <0x2>; > > > + } > > > + L18: cpu@3 { > > > + device_type = "cpu"; > > > + compatible = "sifive,rocket0", "riscv"; > > > + reg = <0x3>; > > > + } > > > + L21: cpu@4 { > > > + device_type = "cpu"; > > > + compatible = "sifive,rocket0", "riscv"; > > > + reg = <0x4>; > > > + } > > > +}; > > > > The labels for the CPUs drew my attention. Is it intentionally random > > (or even specific) or just chosen to show anything can be used as labels ? > > SiFive generates the device tree from RTL directly. So I am not sure if they > assign random numbers or a particular algorithm chooses the label. I tried > to put the exact ones that is available publicly. > > https://github.com/riscv/riscv-device-tree-doc/blob/master/examples/sifive-hifive_unleashed-microsemi.dts Cool, love that. So you don't have the problem I was trying to explain. But I still see the possibility of some other RISC-V vendor copy-pasting from here ;). Anyways it's left to you. -- Regards, Sudeep