Re: [PATCH] regmap: regmap-irq/gpio-max77620: add level-irq support

kbuild test robot
2018-12-10T14:20:26Z

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Hi Matti,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.20-rc6 next-20181207]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Matti-Vaittinen/regmap-regmap-irq-gpio-max77620-add-level-irq-support/20181210-212928
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git for-next
config: x86_64-randconfig-x011-201849 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64

All errors (new ones prefixed by >>):

>> drivers/gpio/gpio-max77620.c:33:40: error: expected '}' before ';' token
.types_supported = IRQ_TYPE_EDGE_BOTH;
^
drivers/gpio/gpio-max77620.c:41:40: error: expected '}' before ';' token
.types_supported = IRQ_TYPE_EDGE_BOTH;
^
drivers/gpio/gpio-max77620.c:49:40: error: expected '}' before ';' token
.types_supported = IRQ_TYPE_EDGE_BOTH;
^
drivers/gpio/gpio-max77620.c:57:40: error: expected '}' before ';' token
.types_supported = IRQ_TYPE_EDGE_BOTH;
^
drivers/gpio/gpio-max77620.c:65:40: error: expected '}' before ';' token
.types_supported = IRQ_TYPE_EDGE_BOTH;
^
drivers/gpio/gpio-max77620.c:73:40: error: expected '}' before ';' token
.types_supported = IRQ_TYPE_EDGE_BOTH;
^
drivers/gpio/gpio-max77620.c:81:40: error: expected '}' before ';' token
.types_supported = IRQ_TYPE_EDGE_BOTH;
^
drivers/gpio/gpio-max77620.c:89:40: error: expected '}' before ';' token
.types_supported = IRQ_TYPE_EDGE_BOTH;
^

vim +33 drivers/gpio/gpio-max77620.c

25
26 static const struct regmap_irq max77620_gpio_irqs[] = {
27 [0] = {
28 .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
29 .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
30 .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
31 .reg_offset = 0,
32 .type_reg_offset = 0,
> 33 .types_supported = IRQ_TYPE_EDGE_BOTH;
34 },
35 [1] = {
36 .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
37 .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
38 .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
39 .reg_offset = 0,
40 .type_reg_offset = 1,
41 .types_supported = IRQ_TYPE_EDGE_BOTH;
42 },
43 [2] = {
44 .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
45 .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
46 .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
47 .reg_offset = 0,
48 .type_reg_offset = 2,
49 .types_supported = IRQ_TYPE_EDGE_BOTH;
50 },
51 [3] = {
52 .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
53 .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
54 .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
55 .reg_offset = 0,
56 .type_reg_offset = 3,
57 .types_supported = IRQ_TYPE_EDGE_BOTH;
58 },
59 [4] = {
60 .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
61 .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
62 .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
63 .reg_offset = 0,
64 .type_reg_offset = 4,
65 .types_supported = IRQ_TYPE_EDGE_BOTH;
66 },
67 [5] = {
68 .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
69 .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
70 .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
71 .reg_offset = 0,
72 .type_reg_offset = 5,
73 .types_supported = IRQ_TYPE_EDGE_BOTH;
74 },
75 [6] = {
76 .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
77 .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
78 .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
79 .reg_offset = 0,
80 .type_reg_offset = 6,
81 .types_supported = IRQ_TYPE_EDGE_BOTH;
82 },
83 [7] = {
84 .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
85 .type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
86 .type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
87 .reg_offset = 0,
88 .type_reg_offset = 7,
89 .types_supported = IRQ_TYPE_EDGE_BOTH;
90 },
91 };
92

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