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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id l6sm2813042otk.51.2018.12.18.07.15.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 07:15:34 -0800 (PST) Date: Tue, 18 Dec 2018 09:15:33 -0600 From: Rob Herring To: Andrey Smirnov Cc: Lorenzo Pieralisi , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , devicetree@vger.kernel.org, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v3 3/3] PCI: imx6: Add support for i.MX8MQ Message-ID: <20181218151533.GA2922@bogus> References: <20181218040702.29231-1-andrew.smirnov@gmail.com> <20181218040702.29231-4-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181218040702.29231-4-andrew.smirnov@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 17, 2018 at 08:07:02PM -0800, Andrey Smirnov wrote: > Add code needed to support i.MX8MQ variant. > > Signed-off-by: Andrey Smirnov > Reviewed-by: Lucas Stach > Cc: Bjorn Helgaas > Cc: Fabio Estevam > Cc: Chris Healy > Cc: Lucas Stach > Cc: Leonard Crestez > Cc: "A.s. Dong" > Cc: Richard Zhu > Cc: Rob Herring > Cc: devicetree@vger.kernel.org > Cc: linux-imx@nxp.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-pci@vger.kernel.org > --- > .../bindings/pci/fsl,imx6q-pcie.txt | 6 +- > drivers/pci/controller/dwc/Kconfig | 4 +- > drivers/pci/controller/dwc/pci-imx6.c | 82 ++++++++++++++++++- > 3 files changed, 87 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > index d514c1f2365f..1a10c313e8d7 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > @@ -9,6 +9,7 @@ Required properties: > - "fsl,imx6sx-pcie", > - "fsl,imx6qp-pcie" > - "fsl,imx7d-pcie" > + - "fsl,imx8mq-pcie" > - reg: base address and length of the PCIe controller > - interrupts: A list of interrupt outputs of the controller. Must contain an > entry for each entry in the interrupt-names property. > @@ -45,7 +46,7 @@ Additional required properties for imx6sx-pcie: > PCIE_PHY power domains > - power-domain-names: Must be "pcie", "pcie_phy" > > -Additional required properties for imx7d-pcie: > +Additional required properties for imx7d-pcie and imx8mq-pcie: > - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain > - resets: Must contain phandles to PCIe-related reset lines exposed by SRC > IP block > @@ -54,6 +55,9 @@ Additional required properties for imx7d-pcie: > - "apps" > - "turnoff" > > +Additional required properties for imx8mq-pcie: > +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1; > + Remove this. If GPR register offset is what you need, then put that into DT. Typically, we'd have a property with iomuxc phandle and offset. Rob