Re: [PATCH 1/1] ARM: STi: Restore secondary CPU's bringup

[Russell King - ARM Linux <linux@armlinux.org.uk>]

On Tue, Dec 18, 2018 at 03:48:13PM +0100, patrice.chotard@st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
> 
> Due to pen_release and boot_lock removal, secondary CPU's bringup
> was broken. Restore CPU's bringup by reworking properly
> .smp_prepare_cpus and .smp_boot_secondary STi callbacks.

Sorry, maybe I don't understand your commit message, but you seem to be
saying that removal of the pen_release and boot_lock broke STi's secondary
CPU bring up?  Please clarify, and explain how that happened.

Thanks.

> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> ---
>  arch/arm/mach-sti/platsmp.c | 31 ++++++++++++++++---------------
>  1 file changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
> index 2166850..9bfc93a 100644
> --- a/arch/arm/mach-sti/platsmp.c
> +++ b/arch/arm/mach-sti/platsmp.c
> @@ -28,8 +28,21 @@
>  
>  #include "smp.h"
>  
> +static u32 __iomem *cpu_strt_ptr;
> +
>  static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
>  {
> +	unsigned long entry_pa = __pa_symbol(secondary_startup);
> +
> +	__raw_writel(entry_pa, cpu_strt_ptr);
> +
> +	/*
> +	 * wmb so that data is actually written
> +	 * before cache flush is done
> +	 */
> +	smp_wmb();
> +	sync_cache_w(cpu_strt_ptr);
> +
>  	/*
>  	 * Send the secondary CPU a soft interrupt, thereby causing
>  	 * it to jump to the secondary entrypoint.
> @@ -43,10 +56,8 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
>  {
>  	struct device_node *np;
>  	void __iomem *scu_base;
> -	u32 __iomem *cpu_strt_ptr;
>  	u32 release_phys;
>  	int cpu;
> -	unsigned long entry_pa = __pa_symbol(secondary_startup);
>  
>  	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
>  
> @@ -74,8 +85,8 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
>  		}
>  
>  		/*
> -		 * holding pen is usually configured in SBC DMEM but can also be
> -		 * in RAM.
> +		 * cpu-release-addr is usually configured in SBC DMEM but can
> +		 * also be in RAM.
>  		 */
>  
>  		if (!memblock_is_memory(release_phys))
> @@ -85,17 +96,7 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
>  			cpu_strt_ptr =
>  				(u32 __iomem *)phys_to_virt(release_phys);
>  
> -		__raw_writel(entry_pa, cpu_strt_ptr);
> -
> -		/*
> -		 * wmb so that data is actually written
> -		 * before cache flush is done
> -		 */
> -		smp_wmb();
> -		sync_cache_w(cpu_strt_ptr);
> -
> -		if (!memblock_is_memory(release_phys))
> -			iounmap(cpu_strt_ptr);
> +		set_cpu_possible(cpu, true);
>  	}
>  }
>  
> -- 
> 1.9.1
> 

-- 
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