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Fri, 21 Dec 2018 11:18:52 -0800 (PST) Received: from localhost ([2620:15c:202:1:75a:3f6e:21d:9374]) by smtp.gmail.com with ESMTPSA id d21sm40390507pgv.37.2018.12.21.11.18.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Dec 2018 11:18:52 -0800 (PST) Date: Fri, 21 Dec 2018 11:18:51 -0800 From: Matthias Kaehlcke To: Taniya Das Cc: Andy Gross , linux-arm-msm@vger.kernel.org, Stephen Boyd , Douglas Anderson , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , david.brown@linaro.org, Mark Rutland , linux-soc@vger.kernel.org, amit.kucheria@linaro.org Subject: Re: [PATCH v2] arm64: dts: sdm845: Add cpufreq device node Message-ID: <20181221191851.GC261387@google.com> References: <1545416063-22552-1-git-send-email-tdas@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1545416063-22552-1-git-send-email-tdas@codeaurora.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 21, 2018 at 11:44:23PM +0530, Taniya Das wrote: > This change adds the cpufreq node as per the bindings example for SDM845. > > Signed-off-by: Taniya Das > Tested-by: Matthias Kaehlcke > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 23a253b..a69a21e 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -99,6 +99,7 @@ > compatible = "qcom,kryo385"; > reg = <0x0 0x0>; > enable-method = "psci"; > + qcom,freq-domain = <&cpufreq_hw 0>; > next-level-cache = <&L2_0>; > L2_0: l2-cache { > compatible = "cache"; > @@ -114,6 +115,7 @@ > compatible = "qcom,kryo385"; > reg = <0x0 0x100>; > enable-method = "psci"; > + qcom,freq-domain = <&cpufreq_hw 0>; > next-level-cache = <&L2_100>; > L2_100: l2-cache { > compatible = "cache"; > @@ -126,6 +128,7 @@ > compatible = "qcom,kryo385"; > reg = <0x0 0x200>; > enable-method = "psci"; > + qcom,freq-domain = <&cpufreq_hw 0>; > next-level-cache = <&L2_200>; > L2_200: l2-cache { > compatible = "cache"; > @@ -138,6 +141,7 @@ > compatible = "qcom,kryo385"; > reg = <0x0 0x300>; > enable-method = "psci"; > + qcom,freq-domain = <&cpufreq_hw 0>; > next-level-cache = <&L2_300>; > L2_300: l2-cache { > compatible = "cache"; > @@ -150,6 +154,7 @@ > compatible = "qcom,kryo385"; > reg = <0x0 0x400>; > enable-method = "psci"; > + qcom,freq-domain = <&cpufreq_hw 1>; > next-level-cache = <&L2_400>; > L2_400: l2-cache { > compatible = "cache"; > @@ -162,6 +167,7 @@ > compatible = "qcom,kryo385"; > reg = <0x0 0x500>; > enable-method = "psci"; > + qcom,freq-domain = <&cpufreq_hw 1>; > next-level-cache = <&L2_500>; > L2_500: l2-cache { > compatible = "cache"; > @@ -174,6 +180,7 @@ > compatible = "qcom,kryo385"; > reg = <0x0 0x600>; > enable-method = "psci"; > + qcom,freq-domain = <&cpufreq_hw 1>; > next-level-cache = <&L2_600>; > L2_600: l2-cache { > compatible = "cache"; > @@ -186,6 +193,7 @@ > compatible = "qcom,kryo385"; > reg = <0x0 0x700>; > enable-method = "psci"; > + qcom,freq-domain = <&cpufreq_hw 1>; > next-level-cache = <&L2_700>; > L2_700: l2-cache { > compatible = "cache"; > @@ -1686,6 +1694,17 @@ > status = "disabled"; > }; > }; > + > + cpufreq_hw: cpufreq@17d43000 { > + compatible = "qcom,cpufreq-hw"; > + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; > + reg-names = "freq-domain0", "freq-domain1"; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; > + clock-names = "xo", "alternate"; > + > + #freq-domain-cells = <1>; > + }; > }; > > thermal-zones { Reviewed-by: Matthias Kaehlcke Thanks Matthias