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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 125sm127586976pfx.159.2019.01.07.23.00.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Jan 2019 23:00:31 -0800 (PST) Date: Mon, 7 Jan 2019 22:59:35 -0800 From: Bjorn Andersson To: Vivek Gautam Cc: joro@8bytes.org, robh+dt@kernel.org, andy.gross@linaro.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, mark.rutland@arm.com, david.brown@linaro.org, linux-kernel@vger.kernel.org, robin.murphy@arm.com, will.deacon@arm.com, dianders@chromium.org Subject: Re: [PATCH v4 2/2] dts: arm64/sdm845: Add node for arm,mmu-500 Message-ID: <20190108065935.GA11536@builder> References: <20181011094930.17010-1-vivek.gautam@codeaurora.org> <20181011094930.17010-3-vivek.gautam@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181011094930.17010-3-vivek.gautam@codeaurora.org> User-Agent: Mutt/1.10.0 (2018-05-17) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu 11 Oct 02:49 PDT 2018, Vivek Gautam wrote: > Add device node for arm,mmu-500 available on sdm845. > This MMU-500 with single TCU and multiple TBU architecture > is shared among all the peripherals except gpu. > Hi Vivek, Applying this patch together with UFS ([1] and [2]) ontop of v5.0-rc1 causes my MTP reboot once the UFSHCD module is inserted and probed. Independently the patches seems to work fine. Do you have any suggestion to why this would be? [1] https://lore.kernel.org/lkml/20181210192826.241350-4-evgreen@chromium.org/ [2] https://lore.kernel.org/lkml/20181210192826.241350-5-evgreen@chromium.org/ Regards, Bjorn > Signed-off-by: Vivek Gautam > --- > > Changes since v3: > - none. > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 72 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index b72bdb0a31a5..0aace729643d 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -1297,6 +1297,78 @@ > cell-index = <0>; > }; > > + apps_smmu: iommu@15000000 { > + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; > + reg = <0x15000000 0x80000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > apss_shared: mailbox@17990000 { > compatible = "qcom,sdm845-apss-shared"; > reg = <0x17990000 0x1000>; > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >