From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40E46C43387 for ; Tue, 8 Jan 2019 12:59:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F418E2087E for ; Tue, 8 Jan 2019 12:59:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727992AbfAHM7b convert rfc822-to-8bit (ORCPT ); Tue, 8 Jan 2019 07:59:31 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:44338 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727558AbfAHM7a (ORCPT ); Tue, 8 Jan 2019 07:59:30 -0500 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x08CxFgn032184 for ; Tue, 8 Jan 2019 07:59:28 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pvthbp9tj-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 07:59:28 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 8 Jan 2019 12:59:22 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x08CxLbw2228674 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Jan 2019 12:59:21 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1380F11C05C; Tue, 8 Jan 2019 12:59:21 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AE1E111C04A; Tue, 8 Jan 2019 12:59:20 +0000 (GMT) Received: from oc2783563651 (unknown [9.152.224.86]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 8 Jan 2019 12:59:20 +0000 (GMT) Date: Tue, 8 Jan 2019 13:59:19 +0100 From: Halil Pasic To: Michael Mueller Cc: KVM Mailing List , Linux-S390 Mailing List , linux-kernel@vger.kernel.org, kvm390-list@tuxmaker.boeblingen.de.ibm.com, Martin Schwidefsky , Heiko Carstens , Christian Borntraeger , Janosch Frank , David Hildenbrand , Cornelia Huck , Pierre Morel Subject: Re: [PATCH v5 13/15] KVM: s390: add function process_gib_alert_list() In-Reply-To: <20181219191756.57973-14-mimu@linux.ibm.com> References: <20181219191756.57973-1-mimu@linux.ibm.com> <20181219191756.57973-14-mimu@linux.ibm.com> Organization: IBM X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.31; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 8BIT X-TM-AS-GCONF: 00 x-cbid: 19010812-0008-0000-0000-000002ACE790 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19010812-0009-0000-0000-00002218F587 Message-Id: <20190108135919.18048dd4@oc2783563651> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-01-08_07:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901080107 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 19 Dec 2018 20:17:54 +0100 Michael Mueller wrote: > This function processes the Gib Alert List (GAL). It is required > to run when either a gib alert interruption has been received or > a gisa that is in the alert list is cleared or dropped. > > The GAL is build up by millicode, when the respective ISC bit is > set in the Interruption Alert Mask (IAM) and an interruption of > that class is observed. > > Signed-off-by: Michael Mueller > --- > arch/s390/kvm/interrupt.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 140 insertions(+) > > diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c > index 48a93f5e5333..03e7ba4f215a 100644 > --- a/arch/s390/kvm/interrupt.c > +++ b/arch/s390/kvm/interrupt.c > @@ -2941,6 +2941,146 @@ int kvm_s390_get_irq_state(struct kvm_vcpu *vcpu, __u8 __user *buf, int len) > return n; > } > > +static int __try_airqs_kick(struct kvm *kvm, u8 ipm) > +{ > + struct kvm_s390_float_interrupt *fi = &kvm->arch.float_int; > + struct kvm_vcpu *vcpu = NULL, *kick_vcpu[MAX_ISC + 1]; > + int online_vcpus = atomic_read(&kvm->online_vcpus); > + u8 ioint_mask, isc_mask, kick_mask = 0x00; > + int vcpu_id, kicked = 0; > + > + /* Loop over vcpus in WAIT state. */ > + for (vcpu_id = find_first_bit(fi->idle_mask, online_vcpus); > + /* Until all pending ISCs have a vcpu open for airqs. */ > + (~kick_mask & ipm) && vcpu_id < online_vcpus; > + vcpu_id = find_next_bit(fi->idle_mask, online_vcpus, vcpu_id)) { > + vcpu = kvm_get_vcpu(kvm, vcpu_id); > + if (psw_ioint_disabled(vcpu)) > + continue; > + ioint_mask = (u8)(vcpu->arch.sie_block->gcr[6] >> 24); > + for (isc_mask = 0x80; isc_mask; isc_mask >>= 1) { > + /* ISC pending in IPM ? */ > + if (!(ipm & isc_mask)) > + continue; > + /* vcpu for this ISC already found ? */ > + if (kick_mask & isc_mask) > + continue; > + /* vcpu open for airq of this ISC ? */ > + if (!(ioint_mask & isc_mask)) > + continue; > + /* use this vcpu (for all ISCs in ioint_mask) */ > + kick_mask |= ioint_mask; > + kick_vcpu[kicked++] = vcpu; Assuming that the vcpu can/will take all ISCs it's currently open for does not seem right. We kind of rely on this assumption here, or? > + } > + } > + > + if (vcpu && ~kick_mask & ipm) > + VM_EVENT(kvm, 4, "gib alert undeliverable isc mask > 0x%02x", > + ~kick_mask & ipm); > + > + for (vcpu_id = 0; vcpu_id < kicked; vcpu_id++) > + kvm_s390_vcpu_wakeup(kick_vcpu[vcpu_id]); > + > + return (online_vcpus != 0) ? kicked : -ENODEV; > +} > + > +static void __floating_airqs_kick(struct kvm *kvm) > +{ > + struct kvm_s390_float_interrupt *fi = &kvm->arch.float_int; > + int online_vcpus, kicked; > + u8 ipm_t0, ipm; > + > + /* Get IPM and return if clean, IAM has been restored. */ > + ipm = get_ipm(kvm->arch.gisa, IRQ_FLAG_IAM); > + if (!ipm) > + return; > +retry: > + ipm_t0 = ipm; > + > + /* Try to kick some vcpus in WAIT state. */ > + kicked = __try_airqs_kick(kvm, ipm); > + if (kicked < 0) > + return; > + > + /* Get IPM and return if clean, IAM has been restored. */ > + ipm = get_ipm(kvm->arch.gisa, IRQ_FLAG_IAM); > + if (!ipm) > + return; > + > + /* Start over, if new ISC bits are pending in IPM. */ > + if ((ipm_t0 ^ ipm) & ~ipm_t0) > + goto retry; > + > + /* > + * Return as we just kicked at least one vcpu in WAIT state > + * open for airqs. The IAM will be restored latest when one > + * of them goes into WAIT or STOP state. > + */ > + if (kicked > 0) > + return; > + > + /* > + * No vcpu was kicked either because no vcpu was in WAIT state > + * or none of the vcpus in WAIT state are open for airqs. > + * Return immediately if no vcpus are in WAIT state. > + * There are vcpus in RUN state. They will process the airqs > + * if not closed for airqs as well. In that case the system will > + * delay airqs until a vcpu decides to take airqs again. > + */ > + online_vcpus = atomic_read(&kvm->online_vcpus); > + if (!bitmap_weight(fi->idle_mask, online_vcpus)) > + return; > + > + /* > + * None of the vcpus in WAIT state take airqs and we might > + * have no running vcpus as at least one vcpu is in WAIT state > + * and IPM is dirty. > + */ > + set_iam(kvm->arch.gisa, kvm->arch.iam); > +} > + > +#define NULL_GISA_ADDR 0x00000000UL > +#define NONE_GISA_ADDR 0x00000001UL > +#define GISA_ADDR_MASK 0xfffff000UL > + > +static void __maybe_unused process_gib_alert_list(void) > +{ > + u32 final, next_alert, origin = 0UL; > + struct kvm_s390_gisa *gisa; > + struct kvm *kvm; > + > + do { > + /* > + * If the NONE_GISA_ADDR is still stored in the alert list > + * origin, we will leave the outer loop. No further GISA has > + * been added to the alert list by millicode while processing > + * the current alert list. > + */ > + final = (origin & NONE_GISA_ADDR); > + /* > + * Cut off the alert list and store the NONE_GISA_ADDR in the > + * alert list origin to avoid further GAL interruptions. > + * A new alert list can be build up by millicode in parallel > + * for guests not in the yet cut-off alert list. When in the > + * final loop, store the NULL_GISA_ADDR instead. This will re- > + * enable GAL interruptions on the host again. > + */ > + origin = xchg(&gib->alert_list_origin, > + (!final) ? NONE_GISA_ADDR : NULL_GISA_ADDR); > + /* Loop through the just cut-off alert list. */ > + while (origin & GISA_ADDR_MASK) { > + gisa = (struct kvm_s390_gisa *)(u64)origin; > + next_alert = gisa->next_alert; > + /* Unlink the GISA from the alert list. */ > + gisa->next_alert = origin; > + kvm = container_of(gisa, struct sie_page2, gisa)->kvm; > + /* Kick suitable vcpus */ > + __floating_airqs_kick(kvm); We may finish handling the alerted gisa with iam not set e.g. via some vcpus kicked but ipm still dirty and some vcpus still in wait, or? >From the comments it seems we speculate on being in a safe state, as these are supposed to return to wait or stop soon-ish, and we will set iam then (See ). I don't quite understand. According to my current understanding we might end up loosing initiative in this scenario. Or am I wrong? Regards, Halil > + origin = next_alert; > + } > + } while (!final); > +} > + > static void nullify_gisa(struct kvm_s390_gisa *gisa) > { > memset(gisa, 0, sizeof(struct kvm_s390_gisa));