Re: [PATCH net-next 5/7] net: phy: marvell10g: Force reading of 2.5/5G PMA extended abilities

Russell King - ARM Linux admin
2019-01-21T13:00:43Z

On Mon, Jan 21, 2019 at 01:29:45PM +0100, Maxime Chevallier wrote:
> Hello Russell,
>
> On Mon, 21 Jan 2019 10:52:06 +0000
> Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:
> >It's entirely possible that the 3310 switches to different hardware
> >blocks for 2.5G and 5G speeds, and reading _just_ the 1.4 register
> >is not sufficient.
>
> I agree with you but in that particular case, I think we are reading
> from the correct device. The datasheet itself says that we should be
> reading 1.4 and 1.11 as we expect, with 2.5G/5G support being set (these
> registers are read-only, and the datasheet's values aren't what we
> actually read).

No, you missed what I was saying.

The 88x3310 is a hybrid device. It contains multiple instances of
each individual device at different offsets in each MMD address space.

For example, there isn't just one PCS in MMD 3, there are three:

offset 0x0000: 10GBASE-T PCS
offset 0x1000: 10GBASE-R, 10GBASE-X, 40GBASE-R PCS
offset 0x2000: 1000baseX-FD PCS

Which get used depends on what is active. For example, on the
Macchiatobin, the PCS at 0x1000 gets used for the SFP port, and
the PCS at 0x0000 gets used for the copper port. The PCS at
0x2000 doesn't ever seem to become active.

MMD 4 (PHYXS) is very similar, and MMD 7 (AN) has four instances.
Different AN instances get used for 10GBASE-T, 10GBASE-KR, SGMII etc.

Each of these blocks either comes from Marvell or another manufacturer.
The 3310 is a mismash of IPs bolted together, with a bunch of routing
between them. It is not simply a Clause 45 compliant PHY (it isn't
compliant, because C45 requires certain registers to be reserved,
but the 3310 has incomplete address decoding - visible as repeats in
the address space of each MMD.)

The exception seems to be the PMA/PMD MMD which I've only discovered
a single instance.

> >The 88x3310 is multiple PHY devices in one package, with a CPU that
> >manages the routing between each individual device.
>
> I also just checked register 3.4 "PCS Speed Ability", and 3.8 "PCS
> Status 2" which also contains informations on 2.5G/5G abilities, but
> there's the same issue here.

What I'm saying is, there is much more to this PHY than just the 802.3
register layout because of there being multiple instances. It _may_
be that a different set of instances gets used to the ones at offset 0
for any particular set of speeds.

I can't look at this at the moment because I am unable to get access to
the 802.3bz specifications - I try to get them through the IEEE get
program website, and I can get to the 802.3 Ethernet specs, click on
either of the 802.3bz amendment 7 links, and I just get a couple of
spinning blobs in Firefox - the page never finishes loading. So, I
can't get the register information for NBASE-T and compare it to the
various MMD instances in the 88x3310.

--
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