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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id n68sm26543831pfb.62.2019.01.22.17.09.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Jan 2019 17:09:32 -0800 (PST) Date: Tue, 22 Jan 2019 17:09:30 -0800 From: Bjorn Andersson To: Doug Anderson Cc: Andy Gross , David Brown , Sibi Sankar , Rob Herring , Mark Rutland , linux-arm-msm , devicetree@vger.kernel.org, LKML Subject: Re: [PATCH v3 03/10] arm64: dts: sdm845: Introduce ADSP and CDSP PAS nodes Message-ID: <20190123010930.GI31919@minitux> References: <20190122055112.30943-1-bjorn.andersson@linaro.org> <20190122055112.30943-4-bjorn.andersson@linaro.org> <20190123002610.GE31919@minitux> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.2 (2019-01-07) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 22 Jan 16:40 PST 2019, Doug Anderson wrote: > Hi, > > On Tue, Jan 22, 2019 at 4:26 PM Bjorn Andersson > wrote: > > > > + clocks = <&xo_board>; > > > > + clock-names = "xo"; > > > > > > I've found that nearly all the places that refer to xo_board are wrong > > > and should actually point to '<&rpmhcc RPMH_CXO_CLK>'. Maybe yours > > > should too? > > > > > > > Yes, xo_board is a fake clock representing the 19.2MHz clock feeding the > > cxo (or cxo2) pad of the SoC. So you're definitely right in that this > > should be referencing the actual 19.2MHz clock. > > > > We've kept referring to this as xo_board, as we don't handle probe > > deferral when gcc will probe earlier than rpmcc in the boot and for > > other non-clock drivers the fear of actually hitting 0 on the refcounter > > for this (you don't want to disable the cxo while running the system). > > Note that, as defined in the device tree, "xo_board" is actually 38.4. > IIUC that is not actually a fake/bogus clock but represents the actual > crystal on the board. There's a divide by 2 in the CPU though so most > peripherals consider "xo" as 19.2. > There's the 38.4MHz XO connected to the PMIC, but the signal going into the CXO_IN pad of the SoC is supposed to come from LNBBCLK1 and be 19.2MHz. > ...OK, confirmed. The actual RF_XO_CLK pin on the board is truly > connected to 38.4. > And the three RF clocks from the PMIC are all ticking at 38.4MHz. The "xo" I need here is the LNBBCLK1 (RPMH_CXO_CLK in clk-rpmh), for the purpose of preventing the root clock to be turned off if apps goes to suspend while the modem is booting, before it has had a chance to tell RPM(h) that it needs it to be on. Regards, Bjorn