linux-next: manual merge of the char-misc tree with the qcom tree

[Stephen Rothwell <sfr@canb.auug.org.au>]

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Hi all,

Today's linux-next merge of the char-misc tree got a conflict in:

  arch/arm64/boot/dts/qcom/sdm845.dtsi

between commits:

  05556681948b ("arm64: dts: sdm845: Add videocc node")
  5b6f186f0abb ("arm64: dts: sdm845: Add rpmh powercontroller node")

from the qcom tree and commit:

  ae0037dbfc5e ("arm64: dts: sdm845: Add interconnect provider DT nodes")

from the char-misc tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0ec827394e92,5179cb94c95b..000000000000
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@@ -7,16 -7,13 +7,17 @@@
  
  #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 +#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
 +#include <dt-bindings/clock/qcom,lpass-sdm845.h>
  #include <dt-bindings/clock/qcom,rpmh.h>
 +#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+ #include <dt-bindings/interconnect/qcom,sdm845.h>
  #include <dt-bindings/interrupt-controller/arm-gic.h>
  #include <dt-bindings/phy/phy-qcom-qusb2.h>
 +#include <dt-bindings/power/qcom-rpmpd.h>
  #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 +#include <dt-bindings/reset/qcom,sdm845-pdc.h>
  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 -#include <dt-bindings/clock/qcom,gcc-sdm845.h>
  
  / {
  	interrupt-parent = <&intc>;
@@@ -2075,55 -1604,10 +2076,60 @@@
  				#clock-cells = <1>;
  			};
  
 +			rpmhpd: power-controller {
 +				compatible = "qcom,sdm845-rpmhpd";
 +				#power-domain-cells = <1>;
 +				operating-points-v2 = <&rpmhpd_opp_table>;
 +
 +				rpmhpd_opp_table: opp-table {
 +					compatible = "operating-points-v2";
 +
 +					rpmhpd_opp_ret: opp1 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
 +					};
 +
 +					rpmhpd_opp_min_svs: opp2 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 +					};
 +
 +					rpmhpd_opp_low_svs: opp3 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 +					};
 +
 +					rpmhpd_opp_svs: opp4 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 +					};
 +
 +					rpmhpd_opp_svs_l1: opp5 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 +					};
 +
 +					rpmhpd_opp_nom: opp6 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 +					};
 +
 +					rpmhpd_opp_nom_l1: opp7 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 +					};
 +
 +					rpmhpd_opp_nom_l2: opp8 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
 +					};
 +
 +					rpmhpd_opp_turbo: opp9 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 +					};
 +
 +					rpmhpd_opp_turbo_l1: opp10 {
 +						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 +					};
 +				};
 +			};
++
+ 			rsc_hlos: interconnect {
+ 				compatible = "qcom,sdm845-rsc-hlos";
+ 				#interconnect-cells = <1>;
+ 			};
  		};
  
  		intc: interrupt-controller@17a00000 {

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