From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4965DC282D9 for ; Wed, 30 Jan 2019 15:49:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1952F218A3 for ; Wed, 30 Jan 2019 15:49:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548863398; bh=+INOyHZAeZt27HReDRQNgCdW/5pwXbyqrHJoIGYAwHA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=T8YTXmr46xDMGo7LjJQYdR4WjJLqr9GlQHttSP+Rpc8hTbGa3EXi+JIICezqNARhr W4u54OcpROFKiCH+1Bfic5LkOVVp+qLDnQAvPhi+eQ+dkk2oj5YL8Y2iOvw3PtUMgX BJ2O/6Ar2NGBHzUCMJveJc1UmO94mUlIsXi4CJWI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731597AbfA3Pt4 (ORCPT ); Wed, 30 Jan 2019 10:49:56 -0500 Received: from mail.kernel.org ([198.145.29.99]:44034 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728943AbfA3Pt4 (ORCPT ); Wed, 30 Jan 2019 10:49:56 -0500 Received: from localhost (unknown [69.71.4.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4063121473; Wed, 30 Jan 2019 15:49:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548863395; bh=+INOyHZAeZt27HReDRQNgCdW/5pwXbyqrHJoIGYAwHA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=f0Gi6IUeLtioxqatr7i0DNPhfTdOzXHsjtPn06LuC5R5Pu9LvHwaiF6cORC215d2O b+pzwQbSR2yn4fc54wZNHqpkt2JyDlmSNYCyv6lGcUF9YjrjthrDD7vcnkDqKIQZ3h SKqtLWr8NnftuEyaPR+kyDo/zw9U2bw9D17VvJJU= Date: Wed, 30 Jan 2019 09:49:50 -0600 From: Bjorn Helgaas To: honghui.zhang@mediatek.com Cc: lorenzo.pieralisi@arm.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, ryder.lee@mediatek.com, youlin.pei@mediatek.com, jianjun.wang@mediatek.com Subject: Re: [PATCH] PCI: Mediatek: Use resource_size function on resource object Message-ID: <20190130154950.GD229773@google.com> References: <1546409033-20412-1-git-send-email-honghui.zhang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1546409033-20412-1-git-send-email-honghui.zhang@mediatek.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 02, 2019 at 02:03:53PM +0800, honghui.zhang@mediatek.com wrote: > From: Honghui Zhang > > drivers/pci/pcie-mediatek.c:720:13-16: WARNING: Suspicious code. resource_size is maybe missing with mem > > Generated by: scripts/coccinelle/api/resource_size.cocci > > Signed-off-by: Honghui Zhang > --- > drivers/pci/controller/pcie-mediatek.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index e307166..0168376 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -654,7 +654,6 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > struct resource *mem = &pcie->mem; > const struct mtk_pcie_soc *soc = port->pcie->soc; > u32 val; > - size_t size; > int err; > > /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ > @@ -706,8 +705,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > mtk_pcie_enable_msi(port); > > /* Set AHB to PCIe translation windows */ > - size = mem->end - mem->start; > - val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size)); > + val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(resource_size(mem))); This is actually a fairly interesting change because it effectively changes this: fls(mem->end - mem->start) to this: fls(mem->end - mem->start + 1) And mem->end is the last valid address, so it changes something like this: fls(0xffff) # == 15 to this: fls(0x10000) # == 16 So while this *looks* like a trivial warning fix, it likely fixes an important bug, and it's worth pointing out what that bug is in the changelog. > writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); > > val = upper_32_bits(mem->start); > -- > 2.6.4 >