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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id r203sm136372oih.11.2019.02.13.12.37.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 12:37:52 -0800 (PST) Date: Wed, 13 Feb 2019 14:37:52 -0600 From: Rob Herring To: Yash Shah Cc: palmer@sifive.com, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, thierry.reding@gmail.com, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, paul.walmsley@sifive.com Subject: Re: [PATCH v6 1/2] pwm: sifive: Add DT documentation for SiFive PWM Controller Message-ID: <20190213203752.GA18326@bogus> References: <1550049978-20705-1-git-send-email-yash.shah@sifive.com> <1550049978-20705-2-git-send-email-yash.shah@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1550049978-20705-2-git-send-email-yash.shah@sifive.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 13, 2019 at 02:56:17PM +0530, Yash Shah wrote: > DT documentation for PWM controller added. > > Signed-off-by: Wesley W. Terpstra > [Atish: Compatible string update] > Signed-off-by: Atish Patra > Signed-off-by: Yash Shah > --- > .../devicetree/bindings/pwm/pwm-sifive.txt | 30 ++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt > new file mode 100644 > index 0000000..3b9c64c > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt > @@ -0,0 +1,30 @@ > +SiFive PWM controller > + > +Unlike most other PWM controllers, the SiFive PWM controller currently only > +supports one period for all channels in the PWM. All PWMs need to run at > +the same period. The period also has significant restrictions on the values > +it can achieve, which the driver rounds to the nearest achievable period. > +PWM RTL that corresponds to the IP block version numbers can be found > +here: > + > +https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm > + > +Required properties: > +- compatible: Should be "sifive,$socname-pwm" and "sifive,pwmX". > + Please refer to sifive-blocks-ip-versioning.txt for details. Please specify what soc and IP version are used. Is sifive,pwm10 valid? > +- reg: physical base address and length of the controller's registers > +- clocks: Should contain a clock identifier for the PWM's parent clock. > +- #pwm-cells: Should be 3. See pwm.txt in this directory > + for a description of the cell format. > +- interrupts: one interrupt per PWM channel > + > +Examples: > + > +pwm: pwm@10020000 { > + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; > + reg = <0x0 0x10020000 0x0 0x1000>; > + clocks = <&tlclk>; > + interrupt-parent = <&plic>; > + interrupts = <42 43 44 45>; > + #pwm-cells = <3>; > +}; > -- > 1.9.1 >