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[91.79.175.49]) by smtp.gmail.com with ESMTPSA id j12sm721202lfg.47.2019.02.22.10.04.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Feb 2019 10:04:36 -0800 (PST) From: Dmitry Osipenko To: Russell King , Thierry Reding , Jonathan Hunter , Robert Yang , =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Cc: linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 7/8] ARM: tegra: Support L2 cache maintenance done via firmware Date: Fri, 22 Feb 2019 20:59:25 +0300 Message-Id: <20190222175926.23366-8-digetx@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222175926.23366-1-digetx@gmail.com> References: <20190222175926.23366-1-digetx@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Trusted Foundations firmware require MMU to be enabled for L2 cache maintenance on Tegra30, hence perform the maintenance early/late on suspend-resume respectively. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 36 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/sleep.S | 11 +++++++---- 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 1ad5719779b0..66c8cd63dd86 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -38,6 +38,7 @@ #include #include #include +#include #include "iomap.h" #include "pm.h" @@ -195,8 +196,27 @@ void tegra_idle_lp2_last(void) cpu_cluster_pm_enter(); suspend_cpu_complex(); + /* + * L2 cache disabling using kernel API only allowed when all + * secondary CPU's are offline. Cache have to be disabled early + * if cache maintenance is done via Trusted Foundations firmware. + * Note that CPUIDLE won't ever enter powergate on Tegra30 if any + * of secondary CPU's is online and this is the LP2 codepath only + * for Tegra20/30. + */ + if (trusted_foundations_registered()) + outer_disable(); + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + /* + * Resume L2 cache if it wasn't re-enabled early during resume, + * which is the case for Tegra30 that has to re-enable the cache + * via firmware call. In other cases cache is already enabled and + * hence re-enabling is a no-op. + */ + outer_resume(); + restore_cpu_complex(); cpu_cluster_pm_exit(); } @@ -340,8 +360,24 @@ static int tegra_suspend_enter(suspend_state_t state) break; } + /* + * Cache have to be disabled early if cache maintenance is done + * via Trusted Foundations firmware. Otherwise this is a no-op, + * like on Tegra114+. + */ + if (trusted_foundations_registered()) + outer_disable(); + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func); + /* + * Resume L2 cache if it wasn't re-enabled early during resume, + * which is the case for Tegra30 that has to re-enable the cache + * via firmware call. In other cases cache is already enabled and + * hence re-enabling is a no-op. + */ + outer_resume(); + switch (mode) { case TEGRA_SUSPEND_LP1: tegra_suspend_exit_lp1(); diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 5e3496753df1..0a8086d5a47a 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -132,10 +132,13 @@ ENTRY(tegra_shut_off_mmu) #ifdef CONFIG_CACHE_L2X0 /* Disable L2 cache */ check_cpu_part_num 0xc09, r9, r10 - movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) - movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) - moveq r3, #0 - streq r3, [r2, #L2X0_CTRL] + retne r0 + + mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000 + ldr r3, [r2, #L2X0_CTRL] + mov r9, #0 + tst r3, #1 + strne r9, [r2, #L2X0_CTRL] #endif ret r0 ENDPROC(tegra_shut_off_mmu) -- 2.20.1