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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id g3sm21724039pgg.41.2019.02.27.10.09.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Feb 2019 10:09:54 -0800 (PST) Date: Wed, 27 Feb 2019 10:09:52 -0800 From: Bjorn Andersson To: Marc Gonzalez Cc: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , MSM , LKML , Can Guo , Vivek Gautam , Jeffrey Hugo , Nicolas Dechesne Subject: Re: [PATCH] phy: qcom: qmp: Add SDM845 PCIe QMP PHY support Message-ID: <20190227180952.GA1803@tuxbook-pro> References: <20190226065919.22218-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.3 (2019-02-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 27 Feb 01:27 PST 2019, Marc Gonzalez wrote: > On 26/02/2019 07:59, Bjorn Andersson wrote: > > > qcom_qmp_phy_init() is extended to support the additional register > > writes needed in PCS MISC and the appropriate sequences and resources > > are defined for SDM845. > > > > Signed-off-by: Bjorn Andersson > > --- > > .../devicetree/bindings/phy/qcom-qmp-phy.txt | 7 + > > drivers/phy/qualcomm/phy-qcom-qmp.c | 160 ++++++++++++++++++ > > drivers/phy/qualcomm/phy-qcom-qmp.h | 12 ++ > > 3 files changed, 179 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > > index 5d181fc3cc18..dd2725a9d3f7 100644 > > --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > > +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > > @@ -11,6 +11,7 @@ Required properties: > > "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, > > "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, > > "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998, > > + "qcom,sdm845-qmp-pcie-phy" for PCIe phy on sdm845, > > "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, > > "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845, > > "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845. > > @@ -48,6 +49,10 @@ Required properties: > > "aux", "cfg_ahb", "ref". > > For "qcom,msm8998-qmp-ufs-phy" must contain: > > "ref", "ref_aux". > > + For "qcom,sdm845-qmp-usb3-phy" must contain: > > + "aux", "cfg_ahb", "ref", "refgen". > > qcom,sdm845-qmp-usb3-phy in a PCIe patch? > Must have forgotten to fix it up after copy pasting the other line, thanks for spotting. > > + For "qcom,sdm845-qmp-usb3-phy" must contain: > > + "aux", "cfg_ahb", "ref", "com_aux". > > qcom,sdm845-qmp-usb3-phy again in a PCIe patch? > Ditto. > > > +static const struct qmp_phy_init_tbl sdm845_pcie_pcs_misc_tbl[] = { > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), > > +}; > > I was thinking I might need to do the same for msm8998, since downstream > tweaks pcs_misc + 0x2c = 0x52 > (dunno if that's QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2) > Yeah, we probably should add the 8998 sequences as well. I haven't been able to compare the two side by side, but it's expected that they will be slightly different. > The thing is, phy driver writes unconditionally to pcs_misc + 0x0c > (QPHY_V3_PCS_MISC_CLAMP_ENABLE). Should that be moved elsewhere? > I spotted this as the only difference in the initialization sequence, but concluded that it seems to work fine as it is. So I left that part intact. Regards, Bjorn