From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCFE0C43381 for ; Sun, 3 Mar 2019 17:14:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8464D20835 for ; Sun, 3 Mar 2019 17:14:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="s8ZuZV2/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726654AbfCCROL (ORCPT ); Sun, 3 Mar 2019 12:14:11 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:42378 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726504AbfCCROL (ORCPT ); Sun, 3 Mar 2019 12:14:11 -0500 Received: by mail-pf1-f195.google.com with SMTP id n74so1280205pfi.9; Sun, 03 Mar 2019 09:14:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S/ZyEhorrdTBL7u6Ya1Op9P6A1v1DuFjJTJQoxPu4VY=; b=s8ZuZV2/I3zwZe/kEfY/j0eXq+/h3U63yAwipL4Q2dB5hrlOhAw1eXik/Ldl2LGqUN Hi7aUatMPx7iUaTBQ/MrX89hc3L5gxmLnm3lPIIQLz4ZCjwRWzxQqlJdHyD3TJwskRTI iHe+S2oP/xYlQeJwEiOapE6gnOSrP1XMp/404RAePQS8UKUDIjrY5xOMGDkFGWtE1kvF L2jpV24u81Z/1ETwSq402YHgAbSyYArH4RiLOYB9qNmZdyJ/5AD/CmLZ4i95IImsE22J KuwIsC4qbrL4CLC1yhPiHV+vkhN2q7v1nHzoY/7Mi+PGz8dhL69vSKhatyeSMb7lDPfo 7Z1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S/ZyEhorrdTBL7u6Ya1Op9P6A1v1DuFjJTJQoxPu4VY=; b=gpdK7Y6Qcyee0MQcq8ZANwspRvbVfMF3jAIhHduQKZUqmG5xVDnuoXjmbAWE/g74eZ Nqg4ceCjpBCJCstCbQGGY7unVZmSD0TS7SYGEHwdK3v7KPde5h/+QTjVCgad7tOPeW+w LWMKzid2cNGx5bZZTemfKexG+pTSvyGThF61y70zOHq7vGbPg+QHwVYph/OI/Jid19k1 2JryJrbsyKxfLlRDRmuRwaJ2aYg1+DeVpQ2KQDK9d2kjq5PQNCxjK9hfuMIxU5JmcxSS PRKU2SCQ7U3iqWzpPq4O4MPurPyLBA+wtLhA1+dJX13c0s3lEpiqTun4ujvFCJUXgDJO J5uA== X-Gm-Message-State: APjAAAUV6jXNVZbcqmlWokCC1Wv6HM7WffVmOBIQGFpCYT21tRyuLWqy LzkcNHePFiZtoqVOYc/+5HE= X-Google-Smtp-Source: APXvYqxfLsmRAPRznfkOu8fnFfnK/wUWohnVxn/0K8ORSBztGGzCLcypK9JtpiFfz6FPWuVpZFC/aw== X-Received: by 2002:a63:d49:: with SMTP id 9mr14576916pgn.27.1551633250262; Sun, 03 Mar 2019 09:14:10 -0800 (PST) Received: from localhost.localdomain (ppp91-79-175-49.pppoe.mtu-net.ru. [91.79.175.49]) by smtp.gmail.com with ESMTPSA id e22sm5349412pfi.126.2019.03.03.09.14.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Mar 2019 09:14:09 -0800 (PST) From: Dmitry Osipenko To: Russell King , Thierry Reding , Jonathan Hunter , Robert Yang , =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Cc: linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 7/7] ARM: tegra: Add firmware calls required for suspend-resume on Tegra30 Date: Sun, 3 Mar 2019 20:12:14 +0300 Message-Id: <20190303171214.24821-8-digetx@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190303171214.24821-1-digetx@gmail.com> References: <20190303171214.24821-1-digetx@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to suspend-resume CPU with Trusted Foundations firmware being present on Tegra30, the LP1/LP2 boot vectors and CPU caches need to be set up using the firmware calls and then suspend code shall avoid re-disabling parts that were disabled by the firmware. Tested-by: Robert Yang Tested-by: Michał Mirosław Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 49 +++++++++++++++++++++++++++++ arch/arm/mach-tegra/reset-handler.S | 26 +++++++++++++++ arch/arm/mach-tegra/sleep.S | 14 ++++++--- 3 files changed, 84 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 1ad5719779b0..abf5f88778f4 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -33,11 +33,13 @@ #include #include +#include #include #include #include #include #include +#include #include "iomap.h" #include "pm.h" @@ -159,6 +161,28 @@ int tegra_cpu_do_idle(void) static int tegra_sleep_cpu(unsigned long v2p) { + /* + * L2 cache disabling using kernel API only allowed when all + * secondary CPU's are offline. Cache have to be disabled with + * MMU-on if cache maintenance is done via Trusted Foundations + * firmware. Note that CPUIDLE won't ever enter powergate on Tegra30 + * if any of secondary CPU's is online and this is the LP2-idle + * code-path only for Tegra20/30. + */ + if (trusted_foundations_registered()) + outer_disable(); + + /* + * Note that besides of setting up CPU reset vector this firmware + * call may also do the following, depending on the FW version: + * 1) Disable L2. But this doesn't matter since we already + * disabled the L2. + * 2) Disable D-cache. This need to be taken into account in + * particular by the tegra_disable_clean_inv_dcache() which + * shall avoid the re-disable. + */ + call_firmware_op(prepare_idle, TF_PM_MODE_LP2); + setup_mm_for_reboot(); tegra_sleep_cpu_finish(v2p); @@ -197,6 +221,14 @@ void tegra_idle_lp2_last(void) cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + /* + * Resume L2 cache if it wasn't re-enabled early during resume, + * which is the case for Tegra30 that has to re-enable the cache + * via firmware call. In other cases cache is already enabled and + * hence re-enabling is a no-op. This is always a no-op on Tegra114+. + */ + outer_resume(); + restore_cpu_complex(); cpu_cluster_pm_exit(); } @@ -215,6 +247,15 @@ enum tegra_suspend_mode tegra_pm_validate_suspend_mode( static int tegra_sleep_core(unsigned long v2p) { + /* + * Cache have to be disabled with MMU-on if cache maintenance is done + * via Trusted Foundations firmware. This is a no-op on Tegra114+. + */ + if (trusted_foundations_registered()) + outer_disable(); + + call_firmware_op(prepare_idle, TF_PM_MODE_LP1); + setup_mm_for_reboot(); tegra_sleep_core_finish(v2p); @@ -342,6 +383,14 @@ static int tegra_suspend_enter(suspend_state_t state) cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func); + /* + * Resume L2 cache if it wasn't re-enabled early during resume, + * which is the case for Tegra30 that has to re-enable the cache + * via firmware call. In other cases cache is already enabled and + * hence re-enabling is a no-op. + */ + outer_resume(); + switch (mode) { case TEGRA_SUSPEND_LP1: tegra_suspend_exit_lp1(); diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 31fb53f9ce13..cd94d7c41fc0 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -76,6 +77,7 @@ ENTRY(tegra_resume) orr r1, r1, #1 str r1, [r0] #endif + bl tegra_resume_trusted_foundations #ifdef CONFIG_CACHE_L2X0 /* L2 cache resume & re-enable */ @@ -88,6 +90,30 @@ end_ca9_scu_l2_resume: b cpu_resume ENDPROC(tegra_resume) + +/* + * tegra_resume_trusted_foundations + * + * Trusted Foundations firmware initialization. + * + * Doesn't return if firmware presents. + * Corrupted registers: r1, r2 + */ +ENTRY(tegra_resume_trusted_foundations) + /* Check whether Trusted Foundations firmware presents. */ + mov32 r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + ldr r1, =__tegra_cpu_reset_handler_data_offset + \ + RESET_DATA(TF_PRESENT) + ldr r1, [r2, r1] + cmp r1, #0 + reteq lr + + .arch_extension sec + /* First call after suspend wakes firmware. No arguments required. */ + smc #0 + + b cpu_resume +ENDPROC(tegra_resume_trusted_foundations) #endif .align L1_CACHE_SHIFT diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 5e3496753df1..1735ded5a812 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -49,8 +49,9 @@ ENTRY(tegra_disable_clean_inv_dcache) /* Disable the D-cache */ mrc p15, 0, r2, c1, c0, 0 + tst r2, #CR_C @ see tegra_sleep_cpu() bic r2, r2, #CR_C - mcr p15, 0, r2, c1, c0, 0 + mcrne p15, 0, r2, c1, c0, 0 isb /* Flush the D-cache */ @@ -132,10 +133,13 @@ ENTRY(tegra_shut_off_mmu) #ifdef CONFIG_CACHE_L2X0 /* Disable L2 cache */ check_cpu_part_num 0xc09, r9, r10 - movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) - movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) - moveq r3, #0 - streq r3, [r2, #L2X0_CTRL] + retne r0 + + mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000 + ldr r3, [r2, #L2X0_CTRL] + tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu() + mov r3, #0 + strne r3, [r2, #L2X0_CTRL] #endif ret r0 ENDPROC(tegra_shut_off_mmu) -- 2.20.1