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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id a34sm2067893otc.46.2019.03.27.13.39.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Mar 2019 13:39:59 -0700 (PDT) Date: Wed, 27 Mar 2019 15:39:59 -0500 From: Rob Herring To: Neil Armstrong Cc: daniel@ffwll.ch, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3] dt-bindings: gpu: add bindings for the ARM Mali Bifrost GPU Message-ID: <20190327203959.GA31523@bogus> References: <20190304105802.6010-1-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190304105802.6010-1-narmstrong@baylibre.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 04, 2019 at 11:58:02AM +0100, Neil Armstrong wrote: > Add the bindings for the Bifrost family of ARM Mali GPUs. > > The Bifrost GPU architecture is similar to the Midgard family, > but with a different Shader Core & Execution Engine structures. > > Bindings are based on the Midgard family bindings, but the inner > architectural changes makes it a separate family needing separate > bindings. > > The Bifrost GPUs are present in a number of recent SoCs, like the > Amlogic G12A Family, and many other vendors. > The Amlogic vendor specific compatible is added to handle the > specific IP integration differences and dependencies. > > Signed-off-by: Neil Armstrong > --- > .../bindings/gpu/arm,mali-bifrost.txt | 90 +++++++++++++++++++ > 1 file changed, 90 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt > > Changes since v2: > - moved to a single compatible since HW is fully discoverable > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt > new file mode 100644 > index 000000000000..e068fccf4ce9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt > @@ -0,0 +1,90 @@ > +ARM Mali Bifrost GPU > +==================== > + > +Required properties: > + > +- compatible : > + * Must contain one the following: > + + "arm,mali-bifrost" Perhaps a note that the specific model/revision is discoverable. > + * which must be preceded by one of the following vendor specifics: > + + "amlogic,meson-g12a-mali" > + > +- reg : Physical base address of the device and length of the register area. > + > +- interrupts : Contains the three IRQ lines required by Mali Bifrost devices. > + > +- interrupt-names : Contains the names of IRQ resources in the order they were > + provided in the interrupts property. Must contain: "job", "mmu", "gpu". Please make the order defined. > + > +Optional properties: > + > +- clocks : Phandle to clock for the Mali Bifrost device. > + > +- mali-supply : Phandle to regulator for the Mali device. Refer to > + Documentation/devicetree/bindings/regulator/regulator.txt for details. > + > +- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt > + for details. > + > +- resets : Phandle of the GPU reset line. > + > +Vendor-specific bindings > +------------------------ > + > +The Mali GPU is integrated very differently from one SoC to > +another. In order to accomodate those differences, you have the option > +to specify one more vendor-specific compatible, among: > + > +- "amlogic,meson-g12a-mali" > + Required properties: > + - resets : Should contain phandles of : > + + GPU reset line > + + GPU APB glue reset line > + > +Example for a Mali-G31: > + > +gpu@ffa30000 { > + compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; > + reg = <0xffe40000 0x10000>; > + interrupts = , > + , > + ; > + interrupt-names = "job", "mmu", "gpu"; > + clocks = <&clk CLKID_MALI>; > + mali-supply = <&vdd_gpu>; > + operating-points-v2 = <&gpu_opp_table>; > + resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; > +}; > + > +gpu_opp_table: opp_table0 { > + compatible = "operating-points-v2"; > + > + opp@533000000 { > + opp-hz = /bits/ 64 <533000000>; > + opp-microvolt = <1250000>; > + }; > + opp@450000000 { > + opp-hz = /bits/ 64 <450000000>; > + opp-microvolt = <1150000>; > + }; > + opp@400000000 { > + opp-hz = /bits/ 64 <400000000>; > + opp-microvolt = <1125000>; > + }; > + opp@350000000 { > + opp-hz = /bits/ 64 <350000000>; > + opp-microvolt = <1075000>; > + }; > + opp@266000000 { > + opp-hz = /bits/ 64 <266000000>; > + opp-microvolt = <1025000>; > + }; > + opp@160000000 { > + opp-hz = /bits/ 64 <160000000>; > + opp-microvolt = <925000>; > + }; > + opp@100000000 { > + opp-hz = /bits/ 64 <100000000>; > + opp-microvolt = <912500>; > + }; > +}; > -- > 2.20.1 >