From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5CB3C43381 for ; Mon, 1 Apr 2019 12:23:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9DB22206C0 for ; Mon, 1 Apr 2019 12:23:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726756AbfDAMXA (ORCPT ); Mon, 1 Apr 2019 08:23:00 -0400 Received: from mga11.intel.com ([192.55.52.93]:5219 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725882AbfDAMXA (ORCPT ); Mon, 1 Apr 2019 08:23:00 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Apr 2019 05:22:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,296,1549958400"; d="scan'208";a="157644970" Received: from smile.fi.intel.com (HELO smile) ([10.237.72.86]) by fmsmga004.fm.intel.com with ESMTP; 01 Apr 2019 05:22:57 -0700 Received: from andy by smile with local (Exim 4.92) (envelope-from ) id 1hAvxo-00056b-KP; Mon, 01 Apr 2019 15:22:56 +0300 Date: Mon, 1 Apr 2019 15:22:56 +0300 From: Andy Shevchenko To: Chris Chiu Cc: Mika Westerberg , Daniel Drake , Heikki Krogerus , Linus Walleij , "open list:PIN CONTROL SUBSYSTEM" , Linux Kernel , Linux Upstreaming Team Subject: Re: [PATCH] pinctrl: intel: save HOSTSW_OWN register over suspend/resume Message-ID: <20190401122256.GF9224@smile.fi.intel.com> References: <20171121120422.GR22431@lahna.fi.intel.com> <20190327172940.GR3622@lahna.fi.intel.com> <20190328091729.GV9224@smile.fi.intel.com> <20190328123444.GX3622@lahna.fi.intel.com> <20190401074953.GQ3622@lahna.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 01, 2019 at 06:41:57PM +0800, Chris Chiu wrote: > On Mon, Apr 1, 2019 at 3:49 PM Mika Westerberg > wrote: > > On Fri, Mar 29, 2019 at 04:38:20PM +0800, Chris Chiu wrote: > > Sure I can but it probably does not happen until end of the week because > > I'm currently busy with something else. > > Thanks for your attention. I don't want to distract you so I'll try to > refine the > patch. It would be a great help if you can help review and give comments. > > Don't know whether if the following patch still get the wrong idea about > your thought. It saves the hostsw_own when GPIO requested, check > if the value differs in resume() and restore if necessary. Please kindly > correct me if any. Thanks Thanks for the patch. My comments below. > diff --git a/drivers/pinctrl/intel/pinctrl-intel.c > b/drivers/pinctrl/intel/pinctrl-intel.c > index 8cda7b535b02..d1cfa5adef9b 100644 > --- a/drivers/pinctrl/intel/pinctrl-intel.c > +++ b/drivers/pinctrl/intel/pinctrl-intel.c > @@ -77,6 +77,7 @@ struct intel_pad_context { > u32 padcfg0; > u32 padcfg1; > u32 padcfg2; > + u32 hostown; This is wrong. We have one register per entire (*) group of pins to keep host ownership. Basically it's a mask. *) if it's <= 32, otherwise there are more registers. But in any case it's 1 bit per pin, and not 32 bits. > for (i = 0; i < pctrl->soc->npins; i++) Thus, the actual actions should mimic what we do for interrupt mask. -- With Best Regards, Andy Shevchenko