Re: [PATCH 05/10] dt-bindings: PCI: tegra: Add device tree support for T194

Vidya Sagar
2019-03-27T10:53:40Z

On 3/27/2019 3:40 PM, Jon Hunter wrote:
>
> On 26/03/2019 15:13, Vidya Sagar wrote:
>> Add support for Tegra194 PCIe controllers. These controllers are based
>> on Synopsys DesignWare core IP.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> .../bindings/pci/nvidia,tegra194-pcie.txt | 209 +++++++++++++++++++++
>> .../devicetree/bindings/phy/phy-tegra194-p2u.txt | 34 ++++
>> 2 files changed, 243 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> new file mode 100644
>> index 000000000000..31527283a0cd
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> @@ -0,0 +1,209 @@
>> +NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
>> +
>> +This PCIe host controller is based on the Synopsis Designware PCIe IP
>> +and thus inherits all the common properties defined in designware-pcie.txt.
>> +
>> +Required properties:
>> +- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie".
>> +- device_type: Must be "pci"
>> +- reg: A list of physical base address and length for each set of controller
>> + registers. Must contain an entry for each entry in the reg-names property.
>> +- reg-names: Must include the following entries:
>> + "appl": Controller's application logic registers
>> + "window1": This is the aperture of controller available under 4GB boundary
>> + (i.e. within 32-bit space). This aperture is typically used for
>> + accessing config space of root port itself and also the connected
>> + endpoints (by appropriately programming internal Address
>> + Translation Unit's (iATU) out bound region) and also to map
>> + prefetchable/non-prefetchable BARs.
>> + "config": As per the definition in designware-pcie.txt
>> + "atu_dma": iATU and DMA register. This is where the iATU (internal Address
>> + Translation Unit) registers of the PCIe core are made available
>> + fow SW access.
>> + "dbi": The aperture where root port's own configuration registers are
>> + available
>> + "window2": This is the larger (compared to window1) aperture available above
>> + 4GB boundary (i.e. in 64-bit space). This is typically used for
>> + mapping prefetchable/non-prefetchable BARs of endpoints
>> +- interrupts: A list of interrupt outputs of the controller. Must contain an
>> + entry for each entry in the interrupt-names property.
>> +- interrupt-names: Must include the following entries:
>> + "intr": The Tegra interrupt that is asserted for controller interrupts
>> + "msi": The Tegra interrupt that is asserted when an MSI is received
>> +- bus-range: Range of bus numbers associated with this controller
>> +- #address-cells: Address representation for root ports (must be 3)
>> + - cell 0 specifies the bus and device numbers of the root port:
>> + [23:16]: bus number
>> + [15:11]: device number
>> + - cell 1 denotes the upper 32 address bits and should be 0
>> + - cell 2 contains the lower 32 address bits and is used to translate to the
>> + CPU address space
>> +- #size-cells: Size representation for root ports (must be 2)
>> +- ranges: Describes the translation of addresses for root ports and standard
>> + PCI regions. The entries must be 7 cells each, where the first three cells
>> + correspond to the address as described for the #address-cells property
>> + above, the fourth and fifth cells are for the physical CPU address to
>> + translate to and the sixth and seventh cells are as described for the
>> + #size-cells property above.
>> + - Entries setup the mapping for the standard I/O, memory and
>> + prefetchable PCI regions. The first cell determines the type of region
>> + that is setup:
>> + - 0x81000000: I/O memory region
>> + - 0x82000000: non-prefetchable memory region
>> + - 0xc2000000: prefetchable memory region
>> + Please refer to the standard PCI bus binding document for a more detailed
>> + explanation.
>> +- #interrupt-cells: Size representation for interrupts (must be 1)
>> +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
>> + Please refer to the standard PCI bus binding document for a more detailed
>> + explanation.
>> +- clocks: Must contain an entry for each entry in clock-names.
>> + See ../clocks/clock-bindings.txt for details.
>> +- clock-names: Must include the following entries:
>> + - core_clk
>> +- resets: Must contain an entry for each entry in reset-names.
>> + See ../reset/reset.txt for details.
>> +- reset-names: Must include the following entries:
>> + - core_apb_rst
>> + - core_rst
>> +- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
>> +- phy-names: Must include an entry for each active lane.
>> + "pcie-p2u-N": where N ranges from 0 to one less than the total number of lanes
>> +- Controller dependent register offsets
>> + - nvidia,event-cntr-ctrl: EVENT_COUNTER_CONTROL reg offset
>> + 0x168 - FPGA
>> + 0x1a8 - C1, C2 and C3
>> + 0x1c4 - C4
>> + 0x1d8 - C0 and C5
>> + - nvidia,event-cntr-data: EVENT_COUNTER_DATA reg offset
>> + 0x16c - FPGA
>> + 0x1ac - C1, C2 and C3
>> + 0x1c8 - C4
>> + 0x1dc - C0 and C5
>> +- nvidia,controller-id : Controller specific ID
>> + 0x0 - C0
>> + 0x1 - C1
>> + 0x2 - C2
>> + 0x3 - C3
>> + 0x4 - C4
>> + 0x5 - C5
>> +- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
>
> I don't see any power-domains listed here. We should have these for T194
> right?
Thanks for catching this.
Yes. PCIe uses power-domains and I'll add that in the future patch.

>
> Cheers
> Jon
>