From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Ingo Molnar <mingo@kernel.org>, Thomas Gleixner <tglx@linutronix.de>
Cc: Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Clark Williams <williams@redhat.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Andi Kleen <ak@linux.intel.com>, Kan Liang <kan.liang@intel.com>,
Arnaldo Carvalho de Melo <acme@redhat.com>
Subject: [PATCH 36/44] perf vendor events intel: Update JakeTown events to v20
Date: Tue, 2 Apr 2019 13:05:41 -0300 [thread overview]
Message-ID: <20190402160549.13544-37-acme@kernel.org> (raw)
In-Reply-To: <20190402160549.13544-1-acme@kernel.org>
From: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/x86/jaketown/cache.json | 6 +++---
.../perf/pmu-events/arch/x86/jaketown/pipeline.json | 12 ++++--------
2 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/perf/pmu-events/arch/x86/jaketown/cache.json
index ee22e4a5e30d..52dc6ef40e63 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json
@@ -31,7 +31,7 @@
},
{
"PEBS": "1",
- "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
+ "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"EventCode": "0xD0",
"Counter": "0,1,2,3",
"UMask": "0x41",
@@ -42,7 +42,7 @@
},
{
"PEBS": "1",
- "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
+ "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"EventCode": "0xD0",
"Counter": "0,1,2,3",
"UMask": "0x42",
@@ -179,7 +179,7 @@
"CounterHTOff": "0,1,2,3"
},
{
- "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier. ",
+ "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
"EventCode": "0x51",
"Counter": "0,1,2,3",
"UMask": "0x1",
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
index 34a519d9bfa0..783a5b4a67b1 100644
--- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json
@@ -1,7 +1,6 @@
[
{
- "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. ",
- "EventCode": "0x00",
+ "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
"Counter": "Fixed counter 1",
"UMask": "0x1",
"EventName": "INST_RETIRED.ANY",
@@ -10,8 +9,7 @@
"CounterHTOff": "Fixed counter 1"
},
{
- "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ",
- "EventCode": "0x00",
+ "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"Counter": "Fixed counter 2",
"UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
@@ -20,8 +18,7 @@
"CounterHTOff": "Fixed counter 2"
},
{
- "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. ",
- "EventCode": "0x00",
+ "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"Counter": "Fixed counter 3",
"UMask": "0x3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
@@ -778,7 +775,7 @@
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
- "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
+ "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
"EventCode": "0x03",
"Counter": "0,1,2,3",
"UMask": "0x2",
@@ -1098,7 +1095,6 @@
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
- "EventCode": "0x00",
"Counter": "Fixed counter 2",
"UMask": "0x2",
"AnyThread": "1",
--
2.20.1
next prev parent reply other threads:[~2019-04-02 16:08 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-02 16:05 [GIT PULL 00/44] perf/core improvements and fixes for 5.2 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 01/44] perf trace: Add 'string' event alias to select syscalls with string args Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 02/44] perf augmented_raw_syscalls: Copy strings from all syscalls with 1st or 2nd string arg Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 03/44] perf augmented_raw_syscalls: Use a PERCPU_ARRAY map to copy more string bytes Arnaldo Carvalho de Melo
2019-04-02 16:44 ` Andrii Nakryiko
2019-04-02 16:05 ` [PATCH 04/44] perf trace beauty renameat: No need to include linux/fs.h Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 05/44] perf tools: Add header defining used namespace struct to event.h Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 06/44] perf list: Fix s390 counter long description for L1D_RO_EXCL_WRITES Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 07/44] perf stat: Revert checks for duration_time Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 08/44] perf stat: Implement duration_time as a proper event Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 09/44] perf evsel: Support printing evsel name for 'duration_time' Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 10/44] perf list: Output tool events Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 11/44] tools lib traceevent: Handle trace_printk() "%px" Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 12/44] tools lib traceevent: Add mono clocks to be parsed in seconds Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 13/44] tools lib traceevent: Implement a new API, tep_list_events_copy() Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 14/44] tools lib traceevent: Add more debugging to see various internal ring buffer entries Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 15/44] tools lib traceevent: Change description of few APIs Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 16/44] tools lib traceevent: Coding style fixes Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 17/44] tools lib traceevent: Implement new traceevent APIs for accessing struct tep_handler fields Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 18/44] tools lib traceevent: Removed unneeded !! and return parenthesis Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 19/44] tools lib traceevent: Remove tep filter trivial APIs Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 20/44] tools lib traceevent: Remove call to exit() from tep_filter_add_filter_str() Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 21/44] tools tools, tools lib traceevent: Make traceevent APIs more consistent Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 22/44] tools lib traceevent: Rename input arguments of libtraceevent APIs from pevent to tep Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 23/44] perf tools, tools lib traceevent: Rename "pevent" member of struct tep_event to "tep" Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 24/44] perf tools, tools lib traceevent: Rename "pevent" member of struct tep_event_filter " Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 25/44] tools lib traceevent: Rename input arguments and local variables of libtraceevent from pevent to tep Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 26/44] tools build: Implement libzstd feature check, LIBZSTD_DIR and NO_LIBZSTD defines Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 27/44] perf record: Implement --mmap-flush=<number> option Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 28/44] perf vendor events intel: Update metrics from TMAM 3.5 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 29/44] perf vendor events intel: Update Broadwell events to v23 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 30/44] perf vendor events intel: Update Broadwell-DE events to v7 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 31/44] perf vendor events intel: Update Skylake events to v42 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 32/44] perf vendor events intel: Update SkylakeX events to v1.12 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 33/44] perf vendor events intel: Update BroadwellX events to v14 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 34/44] perf vendor events intel: Update HaswellX events to v20 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 35/44] perf vendor events intel: Update IvyTown " Arnaldo Carvalho de Melo
2019-04-02 16:05 ` Arnaldo Carvalho de Melo [this message]
2019-04-02 16:05 ` [PATCH 37/44] perf vendor events intel: Update SandyBridge events to v16 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 38/44] perf vendor events intel: Update IvyBridge events to v21 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 39/44] perf vendor events intel: Update Haswell events to v28 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 40/44] perf vendor events intel: Update KnightsLanding events to v9 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 41/44] perf vendor events intel: Update Bonnell to V4 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 42/44] perf vendor events intel: Update Goldmont to v13 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 43/44] perf vendor events intel: Update GoldmontPlus to v1.01 Arnaldo Carvalho de Melo
2019-04-02 16:05 ` [PATCH 44/44] perf vendor events intel: Update Silvermont to v14 Arnaldo Carvalho de Melo
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