[PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events

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* [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events
@ 2019-04-04 23:25 Florian Fainelli
  2019-04-04 23:25 ` [PATCH 1/2] arm64: perf: Group common ARMv8 v3 PMU events in a macro Florian Fainelli
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-04-04 23:25 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, Peter Zijlstra, Ingo Molnar,
	Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
	Namhyung Kim, Will Deacon, Mark Rutland, Catalin Marinas,
	open list:PERFORMANCE EVENTS SUBSYSTEM

Hi all,

This patch series adds support for the Cortex-A53 micro architectural
events that I recently had to use for some debugging exercise.

Events from 0xC0 - 0xD2 are exposed, others could easily be added later
if we wanted to.

Thanks!

Florian Fainelli (2):
  arm64: perf: Group common ARMv8 v3 PMU events in a macro
  arm64: perf: Expose Cortex-A53 micro architectural events

 arch/arm64/kernel/perf_event.c | 241 ++++++++++++++++++++++++---------
 1 file changed, 179 insertions(+), 62 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/2] arm64: perf: Group common ARMv8 v3 PMU events in a macro
  2019-04-04 23:25 [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events Florian Fainelli
@ 2019-04-04 23:25 ` Florian Fainelli
  2019-04-04 23:25 ` [PATCH 2/2] arm64: perf: Expose Cortex-A53 micro architectural events Florian Fainelli
  2019-04-05  9:36 ` [PATCH 0/2] " Robin Murphy
  2 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-04-04 23:25 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, Peter Zijlstra, Ingo Molnar,
	Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
	Namhyung Kim, Will Deacon, Mark Rutland, Catalin Marinas,
	open list:PERFORMANCE EVENTS SUBSYSTEM

In preparation for adding processor specific attributes, group the ARMv8
PMU v3 common events into a macro that can be re-used to fill up an
array of attributes.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm64/kernel/perf_event.c | 123 +++++++++++++++++----------------
 1 file changed, 63 insertions(+), 60 deletions(-)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4addb38bc250..2d30922692b1 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -234,67 +234,70 @@ ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED);
 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE);
 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION);
 
+#define ARMV8_PMUV3_EVENT_ATTRS					\
+	&armv8_event_attr_sw_incr.attr.attr,			\
+	&armv8_event_attr_l1i_cache_refill.attr.attr,		\
+	&armv8_event_attr_l1i_tlb_refill.attr.attr,		\
+	&armv8_event_attr_l1d_cache_refill.attr.attr,		\
+	&armv8_event_attr_l1d_cache.attr.attr,			\
+	&armv8_event_attr_l1d_tlb_refill.attr.attr,		\
+	&armv8_event_attr_ld_retired.attr.attr,			\
+	&armv8_event_attr_st_retired.attr.attr,			\
+	&armv8_event_attr_inst_retired.attr.attr,		\
+	&armv8_event_attr_exc_taken.attr.attr,			\
+	&armv8_event_attr_exc_return.attr.attr,			\
+	&armv8_event_attr_cid_write_retired.attr.attr,		\
+	&armv8_event_attr_pc_write_retired.attr.attr,		\
+	&armv8_event_attr_br_immed_retired.attr.attr,		\
+	&armv8_event_attr_br_return_retired.attr.attr,		\
+	&armv8_event_attr_unaligned_ldst_retired.attr.attr,	\
+	&armv8_event_attr_br_mis_pred.attr.attr,		\
+	&armv8_event_attr_cpu_cycles.attr.attr,			\
+	&armv8_event_attr_br_pred.attr.attr,			\
+	&armv8_event_attr_mem_access.attr.attr,			\
+	&armv8_event_attr_l1i_cache.attr.attr,			\
+	&armv8_event_attr_l1d_cache_wb.attr.attr,		\
+	&armv8_event_attr_l2d_cache.attr.attr,			\
+	&armv8_event_attr_l2d_cache_refill.attr.attr,		\
+	&armv8_event_attr_l2d_cache_wb.attr.attr,		\
+	&armv8_event_attr_bus_access.attr.attr,			\
+	&armv8_event_attr_memory_error.attr.attr,		\
+	&armv8_event_attr_inst_spec.attr.attr,			\
+	&armv8_event_attr_ttbr_write_retired.attr.attr,		\
+	&armv8_event_attr_bus_cycles.attr.attr,			\
+	&armv8_event_attr_l1d_cache_allocate.attr.attr,		\
+	&armv8_event_attr_l2d_cache_allocate.attr.attr,		\
+	&armv8_event_attr_br_retired.attr.attr,			\
+	&armv8_event_attr_br_mis_pred_retired.attr.attr,	\
+	&armv8_event_attr_stall_frontend.attr.attr,		\
+	&armv8_event_attr_stall_backend.attr.attr,		\
+	&armv8_event_attr_l1d_tlb.attr.attr,			\
+	&armv8_event_attr_l1i_tlb.attr.attr,			\
+	&armv8_event_attr_l2i_cache.attr.attr,			\
+	&armv8_event_attr_l2i_cache_refill.attr.attr,		\
+	&armv8_event_attr_l3d_cache_allocate.attr.attr,		\
+	&armv8_event_attr_l3d_cache_refill.attr.attr,		\
+	&armv8_event_attr_l3d_cache.attr.attr,			\
+	&armv8_event_attr_l3d_cache_wb.attr.attr,		\
+	&armv8_event_attr_l2d_tlb_refill.attr.attr,		\
+	&armv8_event_attr_l2i_tlb_refill.attr.attr,		\
+	&armv8_event_attr_l2d_tlb.attr.attr,			\
+	&armv8_event_attr_l2i_tlb.attr.attr,			\
+	&armv8_event_attr_remote_access.attr.attr,		\
+	&armv8_event_attr_ll_cache.attr.attr,			\
+	&armv8_event_attr_ll_cache_miss.attr.attr,		\
+	&armv8_event_attr_dtlb_walk.attr.attr,			\
+	&armv8_event_attr_itlb_walk.attr.attr,			\
+	&armv8_event_attr_ll_cache_rd.attr.attr,		\
+	&armv8_event_attr_ll_cache_miss_rd.attr.attr,		\
+	&armv8_event_attr_remote_access_rd.attr.attr,		\
+	&armv8_event_attr_sample_pop.attr.attr,			\
+	&armv8_event_attr_sample_feed.attr.attr,		\
+	&armv8_event_attr_sample_filtrate.attr.attr,		\
+	&armv8_event_attr_sample_collision.attr.attr,		\
+
 static struct attribute *armv8_pmuv3_event_attrs[] = {
-	&armv8_event_attr_sw_incr.attr.attr,
-	&armv8_event_attr_l1i_cache_refill.attr.attr,
-	&armv8_event_attr_l1i_tlb_refill.attr.attr,
-	&armv8_event_attr_l1d_cache_refill.attr.attr,
-	&armv8_event_attr_l1d_cache.attr.attr,
-	&armv8_event_attr_l1d_tlb_refill.attr.attr,
-	&armv8_event_attr_ld_retired.attr.attr,
-	&armv8_event_attr_st_retired.attr.attr,
-	&armv8_event_attr_inst_retired.attr.attr,
-	&armv8_event_attr_exc_taken.attr.attr,
-	&armv8_event_attr_exc_return.attr.attr,
-	&armv8_event_attr_cid_write_retired.attr.attr,
-	&armv8_event_attr_pc_write_retired.attr.attr,
-	&armv8_event_attr_br_immed_retired.attr.attr,
-	&armv8_event_attr_br_return_retired.attr.attr,
-	&armv8_event_attr_unaligned_ldst_retired.attr.attr,
-	&armv8_event_attr_br_mis_pred.attr.attr,
-	&armv8_event_attr_cpu_cycles.attr.attr,
-	&armv8_event_attr_br_pred.attr.attr,
-	&armv8_event_attr_mem_access.attr.attr,
-	&armv8_event_attr_l1i_cache.attr.attr,
-	&armv8_event_attr_l1d_cache_wb.attr.attr,
-	&armv8_event_attr_l2d_cache.attr.attr,
-	&armv8_event_attr_l2d_cache_refill.attr.attr,
-	&armv8_event_attr_l2d_cache_wb.attr.attr,
-	&armv8_event_attr_bus_access.attr.attr,
-	&armv8_event_attr_memory_error.attr.attr,
-	&armv8_event_attr_inst_spec.attr.attr,
-	&armv8_event_attr_ttbr_write_retired.attr.attr,
-	&armv8_event_attr_bus_cycles.attr.attr,
-	&armv8_event_attr_l1d_cache_allocate.attr.attr,
-	&armv8_event_attr_l2d_cache_allocate.attr.attr,
-	&armv8_event_attr_br_retired.attr.attr,
-	&armv8_event_attr_br_mis_pred_retired.attr.attr,
-	&armv8_event_attr_stall_frontend.attr.attr,
-	&armv8_event_attr_stall_backend.attr.attr,
-	&armv8_event_attr_l1d_tlb.attr.attr,
-	&armv8_event_attr_l1i_tlb.attr.attr,
-	&armv8_event_attr_l2i_cache.attr.attr,
-	&armv8_event_attr_l2i_cache_refill.attr.attr,
-	&armv8_event_attr_l3d_cache_allocate.attr.attr,
-	&armv8_event_attr_l3d_cache_refill.attr.attr,
-	&armv8_event_attr_l3d_cache.attr.attr,
-	&armv8_event_attr_l3d_cache_wb.attr.attr,
-	&armv8_event_attr_l2d_tlb_refill.attr.attr,
-	&armv8_event_attr_l2i_tlb_refill.attr.attr,
-	&armv8_event_attr_l2d_tlb.attr.attr,
-	&armv8_event_attr_l2i_tlb.attr.attr,
-	&armv8_event_attr_remote_access.attr.attr,
-	&armv8_event_attr_ll_cache.attr.attr,
-	&armv8_event_attr_ll_cache_miss.attr.attr,
-	&armv8_event_attr_dtlb_walk.attr.attr,
-	&armv8_event_attr_itlb_walk.attr.attr,
-	&armv8_event_attr_ll_cache_rd.attr.attr,
-	&armv8_event_attr_ll_cache_miss_rd.attr.attr,
-	&armv8_event_attr_remote_access_rd.attr.attr,
-	&armv8_event_attr_sample_pop.attr.attr,
-	&armv8_event_attr_sample_feed.attr.attr,
-	&armv8_event_attr_sample_filtrate.attr.attr,
-	&armv8_event_attr_sample_collision.attr.attr,
+	ARMV8_PMUV3_EVENT_ATTRS
 	NULL,
 };
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 2/2] arm64: perf: Expose Cortex-A53 micro architectural events
  2019-04-04 23:25 [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events Florian Fainelli
  2019-04-04 23:25 ` [PATCH 1/2] arm64: perf: Group common ARMv8 v3 PMU events in a macro Florian Fainelli
@ 2019-04-04 23:25 ` Florian Fainelli
  2019-04-05  9:36 ` [PATCH 0/2] " Robin Murphy
  2 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-04-04 23:25 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, Peter Zijlstra, Ingo Molnar,
	Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
	Namhyung Kim, Will Deacon, Mark Rutland, Catalin Marinas,
	open list:PERFORMANCE EVENTS SUBSYSTEM

Add a variety of useful Cortex-A53 PMU specific events which were
recently found useful during a debug session.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm64/kernel/perf_event.c | 118 ++++++++++++++++++++++++++++++++-
 1 file changed, 116 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 2d30922692b1..ef4105908830 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -31,7 +31,23 @@
 #include <linux/platform_device.h>
 
 /* ARMv8 Cortex-A53 specific event types. */
+#define ARMV8_A53_PERFCTR_EXT_MEM_REQ				0xC0
+#define ARMV8_A53_PERFCTR_NC_EXT_MEM_REQ			0xC1
 #define ARMV8_A53_PERFCTR_PREF_LINEFILL				0xC2
+#define ARMV8_A53_PERFCTR_I_CACHE_THROTTLE			0xC3
+#define ARMV8_A53_PERFCTR_ENT_READ_ALLOC			0xC4
+#define ARMV8_A53_PERFCTR_READ_ALLOC_MODE			0xC5
+#define ARMV8_A53_PERFCTR_PRE_DECODE_ERROR			0xC6
+#define ARMV8_A53_PERFCTR_DATA_WR_STALL				0xC7
+#define ARMV8_A53_PERFCTR_SCU_SNOOP_OTHER_CPU			0xC8
+#define ARMV8_A53_PERFCTR_COND_BRANCH_EXEC			0xC9
+#define ARMV8_A53_PERFCTR_INDIR_BRANCH_MISPRED			0xCA
+#define ARMV8_A53_PERFCTR_INDIR_BRANCH_MISPRED_COMP		0xCB
+#define ARMV8_A53_PERFCTR_COND_BRANCH_MISPRED			0xCC
+#define ARMV8_A53_PERFCTR_L1I_CACHE_MEM_ERR			0xD0
+#define ARMV8_A53_PERFCTR_L1D_CACHE_MEM_ERR			0xD1
+#define ARMV8_A53_PERFCTR_TLB_MEM_ERR				0xD2
+#define ARMV8_A53_PERFCTR_MAX_EVENTS				0xD3
 
 /* ARMv8 Cavium ThunderX specific event types. */
 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST			0xE9
@@ -349,6 +365,82 @@ static struct attribute_group armv8_pmuv3_format_attr_group = {
 	.attrs = armv8_pmuv3_format_attrs,
 };
 
+#define ARMV8_CORTEXA53_EVENT_ATTR_RESOLVE(m) #m
+#define ARMV8_CORTEXA53_EVENT_ATTR(name, config) \
+	PMU_EVENT_ATTR(name, armv8_cortex_a53_event_attr_##name, \
+		       config, armv8pmu_events_sysfs_show)
+
+ARMV8_CORTEXA53_EVENT_ATTR(ext_mem_req, ARMV8_A53_PERFCTR_EXT_MEM_REQ);
+ARMV8_CORTEXA53_EVENT_ATTR(nc_ext_mem_req, ARMV8_A53_PERFCTR_NC_EXT_MEM_REQ);
+ARMV8_CORTEXA53_EVENT_ATTR(pref_linefill, ARMV8_A53_PERFCTR_PREF_LINEFILL);
+ARMV8_CORTEXA53_EVENT_ATTR(i_cache_throttle, ARMV8_A53_PERFCTR_I_CACHE_THROTTLE);
+ARMV8_CORTEXA53_EVENT_ATTR(enter_read_allocate, ARMV8_A53_PERFCTR_ENT_READ_ALLOC);
+ARMV8_CORTEXA53_EVENT_ATTR(read_allocate_mode, ARMV8_A53_PERFCTR_READ_ALLOC_MODE);
+ARMV8_CORTEXA53_EVENT_ATTR(pre_decode_error, ARMV8_A53_PERFCTR_PRE_DECODE_ERROR);
+ARMV8_CORTEXA53_EVENT_ATTR(data_write_stall, ARMV8_A53_PERFCTR_DATA_WR_STALL);
+ARMV8_CORTEXA53_EVENT_ATTR(scu_snoop_other_cpu, ARMV8_A53_PERFCTR_SCU_SNOOP_OTHER_CPU);
+ARMV8_CORTEXA53_EVENT_ATTR(cond_branch_exec, ARMV8_A53_PERFCTR_COND_BRANCH_EXEC);
+ARMV8_CORTEXA53_EVENT_ATTR(indir_br_pred, ARMV8_A53_PERFCTR_INDIR_BRANCH_MISPRED);
+ARMV8_CORTEXA53_EVENT_ATTR(indir_br_pred_comp, ARMV8_A53_PERFCTR_INDIR_BRANCH_MISPRED_COMP);
+ARMV8_CORTEXA53_EVENT_ATTR(cond_br_mis_pred, ARMV8_A53_PERFCTR_COND_BRANCH_MISPRED);
+ARMV8_CORTEXA53_EVENT_ATTR(l1i_cache_mem_err, ARMV8_A53_PERFCTR_L1I_CACHE_MEM_ERR);
+ARMV8_CORTEXA53_EVENT_ATTR(l1d_cache_mem_err, ARMV8_A53_PERFCTR_L1D_CACHE_MEM_ERR);
+ARMV8_CORTEXA53_EVENT_ATTR(tlb_mem_err, ARMV8_A53_PERFCTR_TLB_MEM_ERR);
+
+static struct attribute *armv8_cortex_a53_event_attrs[] = {
+	ARMV8_PMUV3_EVENT_ATTRS
+	&armv8_cortex_a53_event_attr_ext_mem_req.attr.attr,
+	&armv8_cortex_a53_event_attr_nc_ext_mem_req.attr.attr,
+	&armv8_cortex_a53_event_attr_pref_linefill.attr.attr,
+	&armv8_cortex_a53_event_attr_i_cache_throttle.attr.attr,
+	&armv8_cortex_a53_event_attr_enter_read_allocate.attr.attr,
+	&armv8_cortex_a53_event_attr_read_allocate_mode.attr.attr,
+	&armv8_cortex_a53_event_attr_pre_decode_error.attr.attr,
+	&armv8_cortex_a53_event_attr_data_write_stall.attr.attr,
+	&armv8_cortex_a53_event_attr_scu_snoop_other_cpu.attr.attr,
+	&armv8_cortex_a53_event_attr_cond_branch_exec.attr.attr,
+	&armv8_cortex_a53_event_attr_indir_br_pred.attr.attr,
+	&armv8_cortex_a53_event_attr_indir_br_pred_comp.attr.attr,
+	&armv8_cortex_a53_event_attr_cond_br_mis_pred.attr.attr,
+	&armv8_cortex_a53_event_attr_l1i_cache_mem_err.attr.attr,
+	&armv8_cortex_a53_event_attr_l1d_cache_mem_err.attr.attr,
+	&armv8_cortex_a53_event_attr_tlb_mem_err.attr.attr,
+	NULL
+};
+
+static umode_t
+armv8_cortex_a53_pmu_event_attr_is_visible(struct kobject *kobj,
+					   struct attribute *attr, int unused)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct pmu *pmu = dev_get_drvdata(dev);
+	struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
+	struct perf_pmu_events_attr *pmu_attr;
+
+	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
+
+	if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
+	    test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
+		return attr->mode;
+
+	if (pmu_attr->id >= ARMV8_A53_PERFCTR_EXT_MEM_REQ &&
+	    pmu_attr->id < ARMV8_A53_PERFCTR_MAX_EVENTS)
+		return attr->mode;
+
+	pmu_attr->id -= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
+	if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
+	    test_bit(pmu_attr->id, cpu_pmu->pmceid_ext_bitmap))
+		return attr->mode;
+
+	return 0;
+}
+
+static struct attribute_group armv8_cortex_a53_events_attr_group = {
+	.name = "events",
+	.attrs = armv8_cortex_a53_event_attrs,
+	.is_visible = armv8_cortex_a53_pmu_event_attr_is_visible,
+};
+
 /*
  * Perf Events' indices
  */
@@ -910,7 +1002,29 @@ static int armv8_pmuv3_map_event(struct perf_event *event)
 
 static int armv8_a53_map_event(struct perf_event *event)
 {
-	return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
+	int hw_event_id;
+	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+
+	hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
+				       &armv8_pmuv3_perf_cache_map,
+				       ARMV8_PMU_EVTYPE_EVENT);
+
+	if (armv8pmu_event_is_64bit(event))
+		event->hw.flags |= ARMPMU_EVT_64BIT;
+
+	/* Only expose micro/arch events supported by this PMU */
+	if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
+	    && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
+		return hw_event_id;
+	}
+
+	/* Expose Cortex-A53 specific events */
+	if (hw_event_id >= ARMV8_A53_PERFCTR_EXT_MEM_REQ &&
+	    hw_event_id <= ARMV8_A53_PERFCTR_MAX_EVENTS)
+		return hw_event_id;
+
+	return armpmu_map_event(event, NULL, &armv8_a53_perf_cache_map,
+				ARMV8_PMU_EVTYPE_EVENT);
 }
 
 static int armv8_a57_map_event(struct perf_event *event)
@@ -1057,7 +1171,7 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
 	cpu_pmu->name			= "armv8_cortex_a53";
 	cpu_pmu->map_event		= armv8_a53_map_event;
 	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
-		&armv8_pmuv3_events_attr_group;
+		&armv8_cortex_a53_events_attr_group;
 	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
 		&armv8_pmuv3_format_attr_group;
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events
  2019-04-04 23:25 [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events Florian Fainelli
  2019-04-04 23:25 ` [PATCH 1/2] arm64: perf: Group common ARMv8 v3 PMU events in a macro Florian Fainelli
  2019-04-04 23:25 ` [PATCH 2/2] arm64: perf: Expose Cortex-A53 micro architectural events Florian Fainelli
@ 2019-04-05  9:36 ` Robin Murphy
  2019-04-05 12:36   ` Jiri Olsa
  2 siblings, 1 reply; 6+ messages in thread
From: Robin Murphy @ 2019-04-05  9:36 UTC (permalink / raw)
  To: Florian Fainelli, linux-arm-kernel
  Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, Will Deacon,
	open list:PERFORMANCE EVENTS SUBSYSTEM, Arnaldo Carvalho de Melo,
	Alexander Shishkin, Ingo Molnar, Namhyung Kim, Jiri Olsa

Hi Florian,

On 05/04/2019 00:25, Florian Fainelli wrote:
> Hi all,
> 
> This patch series adds support for the Cortex-A53 micro architectural
> events that I recently had to use for some debugging exercise.
> 
> Events from 0xC0 - 0xD2 are exposed, others could easily be added later
> if we wanted to.

As far as I'm aware (which admittedly is not all-the-way far) these 
events should already be understood by userspace, per 
tools/perf/pmu-events/arch/arm64/arm/cortex-a53/* - is there a specific 
reason to need in-kernel definitions?

Robin.

> 
> Thanks!
> 
> Florian Fainelli (2):
>    arm64: perf: Group common ARMv8 v3 PMU events in a macro
>    arm64: perf: Expose Cortex-A53 micro architectural events
> 
>   arch/arm64/kernel/perf_event.c | 241 ++++++++++++++++++++++++---------
>   1 file changed, 179 insertions(+), 62 deletions(-)
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events
  2019-04-05  9:36 ` [PATCH 0/2] " Robin Murphy
@ 2019-04-05 12:36   ` Jiri Olsa
  2019-04-05 16:14     ` Florian Fainelli
  0 siblings, 1 reply; 6+ messages in thread
From: Jiri Olsa @ 2019-04-05 12:36 UTC (permalink / raw)
  To: Robin Murphy
  Cc: Florian Fainelli, linux-arm-kernel, Mark Rutland, Peter Zijlstra,
	Catalin Marinas, Will Deacon,
	open list:PERFORMANCE EVENTS SUBSYSTEM, Arnaldo Carvalho de Melo,
	Alexander Shishkin, Ingo Molnar, Namhyung Kim

On Fri, Apr 05, 2019 at 10:36:20AM +0100, Robin Murphy wrote:
> Hi Florian,
> 
> On 05/04/2019 00:25, Florian Fainelli wrote:
> > Hi all,
> > 
> > This patch series adds support for the Cortex-A53 micro architectural
> > events that I recently had to use for some debugging exercise.
> > 
> > Events from 0xC0 - 0xD2 are exposed, others could easily be added later
> > if we wanted to.
> 
> As far as I'm aware (which admittedly is not all-the-way far) these events
> should already be understood by userspace, per
> tools/perf/pmu-events/arch/arm64/arm/cortex-a53/* - is there a specific
> reason to need in-kernel definitions?

right, we store events in perf tools in json files, please
check commits changelogs under tools/perf/pmu-events/arch

jirka

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events
  2019-04-05 12:36   ` Jiri Olsa
@ 2019-04-05 16:14     ` Florian Fainelli
  0 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-04-05 16:14 UTC (permalink / raw)
  To: Jiri Olsa, Robin Murphy
  Cc: linux-arm-kernel, Mark Rutland, Peter Zijlstra, Catalin Marinas,
	Will Deacon, open list:PERFORMANCE EVENTS SUBSYSTEM,
	Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
	Namhyung Kim

On 4/5/19 5:36 AM, Jiri Olsa wrote:
> On Fri, Apr 05, 2019 at 10:36:20AM +0100, Robin Murphy wrote:
>> Hi Florian,
>>
>> On 05/04/2019 00:25, Florian Fainelli wrote:
>>> Hi all,
>>>
>>> This patch series adds support for the Cortex-A53 micro architectural
>>> events that I recently had to use for some debugging exercise.
>>>
>>> Events from 0xC0 - 0xD2 are exposed, others could easily be added later
>>> if we wanted to.
>>
>> As far as I'm aware (which admittedly is not all-the-way far) these events
>> should already be understood by userspace, per
>> tools/perf/pmu-events/arch/arm64/arm/cortex-a53/* - is there a specific
>> reason to need in-kernel definitions?
> 
> right, we store events in perf tools in json files, please
> check commits changelogs under tools/perf/pmu-events/arch

Whoops, indeed no reason for making them part of the kernel, I will
investigate why the build system did not copy those files and update
them as necessary, thanks both for your feedback.
-- 
Florian

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2019-04-05 16:15 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-04-04 23:25 [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events Florian Fainelli
2019-04-04 23:25 ` [PATCH 1/2] arm64: perf: Group common ARMv8 v3 PMU events in a macro Florian Fainelli
2019-04-04 23:25 ` [PATCH 2/2] arm64: perf: Expose Cortex-A53 micro architectural events Florian Fainelli
2019-04-05  9:36 ` [PATCH 0/2] " Robin Murphy
2019-04-05 12:36   ` Jiri Olsa
2019-04-05 16:14     ` Florian Fainelli

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