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[94.29.35.107]) by smtp.gmail.com with ESMTPSA id m25sm63142091pfa.175.2019.04.14.13.29.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 14 Apr 2019 13:29:15 -0700 (PDT) From: Dmitry Osipenko To: Rob Herring , Mark Rutland , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter , Joseph Lo Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/4] memory: tegra: Introduce Tegra30 EMC driver Date: Sun, 14 Apr 2019 23:20:05 +0300 Message-Id: <20190414202009.31268-1-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, This series introduces driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. The driver was tested using the ACTMON devfreq driver that performs memory frequency scaling based on memory-usage load. Please also note that this patchset is based on this series: https://www.spinics.net/lists/linux-tegra/msg39687.html Changelog: v2: - Added support for changing MC clock diver configuration based on Memory Controller (MC) configuration which is part of the memory timing. - Merged the "Add custom EMC clock implementation" patch into this series because the "Introduce Tegra30 EMC driver" patch directly depends on it. Please note that Tegra20 EMC driver will need to be adapted for the clock changes as well, I'll send out the Tegra20 patches after this series will be applied because of some other dependencies (devfreq) and because the temporary breakage won't be critical (driver will just error out on probe). - EMC driver now performs MC configuration validation by checking that the number of MC / EMC timings matches and that the timings rate is the same. - EMC driver now supports timings that want to change the MC clock configuration. - Other minor prettifying changes of the code. Dmitry Osipenko (4): clk: tegra20/30: Add custom EMC clock implementation dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller memory: tegra: Introduce Tegra30 EMC driver ARM: dts: tegra30: Add External Memory Controller node .../memory-controllers/nvidia,tegra30-emc.txt | 257 ++++ arch/arm/boot/dts/tegra30.dtsi | 11 + drivers/clk/tegra/Makefile | 2 + drivers/clk/tegra/clk-tegra20-emc.c | 307 +++++ drivers/clk/tegra/clk-tegra20.c | 51 +- drivers/clk/tegra/clk-tegra30.c | 35 +- drivers/clk/tegra/clk.h | 6 + drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 3 - drivers/memory/tegra/mc.h | 30 +- drivers/memory/tegra/tegra30-emc.c | 1159 +++++++++++++++++ drivers/memory/tegra/tegra30.c | 44 + include/linux/clk/tegra.h | 6 + 14 files changed, 1860 insertions(+), 62 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.txt create mode 100644 drivers/clk/tegra/clk-tegra20-emc.c create mode 100644 drivers/memory/tegra/tegra30-emc.c -- 2.21.0