From: Andrea Parri <andrea.parri@amarulasolutions.com>
To: "Paul E. McKenney" <paulmck@linux.ibm.com>
Cc: Alan Stern <stern@rowland.harvard.edu>,
LKMM Maintainers -- Akira Yokosawa <akiyks@gmail.com>,
Boqun Feng <boqun.feng@gmail.com>,
Daniel Lustig <dlustig@nvidia.com>,
David Howells <dhowells@redhat.com>,
Jade Alglave <j.alglave@ucl.ac.uk>,
Luc Maranget <luc.maranget@inria.fr>,
Nicholas Piggin <npiggin@gmail.com>,
Peter Zijlstra <peterz@infradead.org>,
Will Deacon <will.deacon@arm.com>,
Daniel Kroening <kroening@cs.ox.ac.uk>,
Kernel development list <linux-kernel@vger.kernel.org>
Subject: Re: Adding plain accesses and detecting data races in the LKMM
Date: Thu, 18 Apr 2019 14:54:12 +0200 [thread overview]
Message-ID: <20190418125412.GA10817@andrea> (raw)
In-Reply-To: <20190415133535.GU14111@linux.ibm.com>
> Another question is "should the kernel permit smp_mb__{before,after}*()
> anywhere other than immediately before or after the primitive being
> strengthened?"
Mmh, I do think that keeping these barriers "immediately before or after
the primitive being strengthened" is a good practice (readability, and
all that), if this is what you're suggesting.
However, a first auditing of the callsites showed that this practice is
in fact not always applied, notably... ;-)
kernel/rcu/tree_exp.h:sync_exp_work_done
kernel/sched/cpupri.c:cpupri_set
So there appear, at least, to be some exceptions/reasons for not always
following it? Thoughts?
BTW, while auditing these callsites, I've stumbled across the following
snippet (from kernel/futex.c):
*futex = newval;
sys_futex(WAKE, futex);
futex_wake(futex);
smp_mb(); (B)
if (waiters)
...
where B is actually (c.f., futex_get_mm()):
atomic_inc(...->mm_count);
smp_mb__after_atomic();
It seems worth mentioning the fact that, AFAICT, this sequence does not
necessarily provide ordering when plain accesses are involved: consider,
e.g., the following variant of the snippet:
A:*x = 1;
/*
* I've "ignored" the syscall, which should provide
* (at least) a compiler barrier...
*/
atomic_inc(u);
smp_mb__after_atomic();
B:r0 = *y;
On x86, AFAICT, the compiler can do this:
atomic_inc(u);
A:*x = 1;
smp_mb__after_atomic();
B:r0 = *y;
(the implementation of atomic_inc() contains no compiler barrier), then
the CPU can "reorder" A and B (smp_mb__after_atomic() being #defined to
a compiler barrier).
The mips implementation seems also affected by such "reorderings": I am
not familiar with this implementation but, AFAICT, it does not enforce
ordering from A to B in the following snippet:
A:*x = 1;
atomic_inc(u);
smp_mb__after_atomic();
B:WRITE_ONCE(*y, 1);
when CONFIG_WEAK_ORDERING=y, CONFIG_WEAK_REORDERING_BEYOND_LLSC=n.
Do these observations make sense to you? Thoughts?
Andrea
next prev parent reply other threads:[~2019-04-18 12:54 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 19:38 Adding plain accesses and detecting data races in the LKMM Alan Stern
2019-04-02 14:42 ` Andrea Parri
2019-04-02 18:06 ` Alan Stern
2019-04-06 0:49 ` Andrea Parri
2019-04-06 16:03 ` Alan Stern
2019-04-08 5:51 ` Andrea Parri
2019-04-08 14:18 ` Alan Stern
2019-04-09 1:36 ` Andrea Parri
2019-04-09 15:01 ` Paul E. McKenney
2019-04-13 21:39 ` Andrea Parri
2019-04-15 13:35 ` Paul E. McKenney
2019-04-15 13:50 ` Alan Stern
2019-04-15 13:53 ` Paul E. McKenney
2019-04-18 12:54 ` Andrea Parri [this message]
2019-04-18 17:44 ` Alan Stern
2019-04-18 18:39 ` Paul E. McKenney
2019-04-18 20:19 ` Alan Stern
2019-04-19 0:53 ` Andrea Parri
2019-04-19 12:47 ` Paul E. McKenney
2019-04-19 14:34 ` Alan Stern
2019-04-19 17:17 ` Paul E. McKenney
2019-04-19 15:06 ` Akira Yokosawa
2019-04-19 16:37 ` Andrea Parri
2019-04-19 18:06 ` Paul E. McKenney
2019-04-20 14:50 ` Akira Yokosawa
2019-04-21 19:38 ` Paul E. McKenney
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