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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id f18sm13702399otl.51.2019.04.29.16.13.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Apr 2019 16:13:16 -0700 (PDT) Date: Mon, 29 Apr 2019 18:13:16 -0500 From: Rob Herring To: Fabien Dessenne Cc: Mark Rutland , Maxime Coquelin , Alexandre Torgue , Ohad Ben-Cohen , Bjorn Andersson , devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, Loic Pallardy , Arnaud Pouliquen , Ludovic Barre , Benjamin Gaignard Subject: Re: [PATCH v2 1/8] dt-bindings: stm32: add bindings for ML-AHB interconnect Message-ID: <20190429231316.GA13995@bogus> References: <1555426699-5340-1-git-send-email-fabien.dessenne@st.com> <1555426699-5340-2-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1555426699-5340-2-git-send-email-fabien.dessenne@st.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 16, 2019 at 04:58:12PM +0200, Fabien Dessenne wrote: > Document the ML-AHB interconnect for stm32 SoCs. > > Signed-off-by: Fabien Dessenne > --- > .../devicetree/bindings/arm/stm32/mlahb.txt | 37 ++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/stm32/mlahb.txt > > diff --git a/Documentation/devicetree/bindings/arm/stm32/mlahb.txt b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt > new file mode 100644 > index 0000000..a36458a > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/stm32/mlahb.txt > @@ -0,0 +1,37 @@ > +ML-AHB interconnect bindings > + > +These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects > +a Cortex-M subsystem with dedicated memories. > +The MCU SRAM and RETRAM memory parts can be accessed through different addresses > +(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the > +Cortex-M firmware accesses among those ports allows to tune the system > +performance. > + > +[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf > +[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping > + > +Required properties: > +- compatible: should be "simple-bus" > +- dma-ranges: describes memory addresses translation between the local CPU and > + the remote Cortex-M processor. Each memory region, is declared with > + 3 parameters: > + - param 1: device base address (Cortex-M processor address) > + - param 2: physical base address (local CPU address) > + - param 3: size of the memory region. > + > +The Cortex-M remote processor accessed via the mlahb interconnect is described > +by a child node. > + > +Example: > +mlahb { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + dma-ranges = <0x00000000 0x38000000 0x10000>, > + <0x10000000 0x10000000 0x60000>, > + <0x30000000 0x30000000 0x60000>; > + > + m4_rproc: m4@0 { '0' is a cpu address given there's no 'ranges' now for translating cpu addresses. I think you want it to be 0x38000000 instead. > + ... > + }; > +}; > -- > 2.7.4 >