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[94.29.35.107]) by smtp.gmail.com with ESMTPSA id g13sm1581649lfh.49.2019.05.05.09.25.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 05 May 2019 09:25:19 -0700 (PDT) From: Dmitry Osipenko To: Daniel Lezcano , Thomas Gleixner , Joseph Lo , Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] clocksource/drivers/tegra: Minor code clean up Date: Sun, 5 May 2019 19:24:35 +0300 Message-Id: <20190505162436.23125-7-digetx@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190505162436.23125-1-digetx@gmail.com> References: <20190505162436.23125-1-digetx@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Correct typo and use proper upper casing for acronyms in the comments, use common style for error messages, prepend error messages with "tegra-timer:", add error message for cpuhp_setup_state() failure and clean up whitespaces in the code to fix checkpatch warnings. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/timer-tegra20.c | 43 ++++++++++++++++------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 7c06c0335fe3..47ef8c9aa0ba 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -15,6 +15,8 @@ * */ +#define pr_fmt(fmt) "tegra-timer: " fmt + #include #include #include @@ -30,13 +32,13 @@ #include "timer-of.h" -#define RTC_SECONDS 0x08 -#define RTC_SHADOW_SECONDS 0x0c -#define RTC_MILLISECONDS 0x10 +#define RTC_SECONDS 0x08 +#define RTC_SHADOW_SECONDS 0x0c +#define RTC_MILLISECONDS 0x10 -#define TIMERUS_CNTR_1US 0x10 -#define TIMERUS_USEC_CFG 0x14 -#define TIMERUS_CNTR_FREEZE 0x4c +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 +#define TIMERUS_CNTR_FREEZE 0x4c #define TIMER_PTV 0x0 #define TIMER_PTV_EN BIT(31) @@ -57,7 +59,7 @@ static u32 usec_config; static void __iomem *timer_reg_base; static int tegra_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) + struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); @@ -176,15 +178,17 @@ static struct timer_of suspend_rtc_to = { /* * tegra_rtc_read - Reads the Tegra RTC registers - * Care must be taken that this funciton is not called while the + * Care must be taken that this function is not called while the * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); + return (u64)s * MSEC_PER_SEC + ms; } @@ -229,7 +233,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); - if (ret < 0) + if (ret) goto out; timer_reg_base = timer_of_base(to); @@ -288,8 +292,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { - pr_err("%s: can't map IRQ for CPU%d\n", - __func__, cpu); + pr_err("failed to map irq for cpu%d\n", cpu); ret = -EINVAL; goto out_irq; } @@ -299,8 +302,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) IRQF_TIMER | IRQF_NOBALANCING, cpu_to->clkevt.name, &cpu_to->clkevt); if (ret) { - pr_err("%s: cannot setup irq %d for CPU%d\n", - __func__, cpu_to->clkevt.irq, cpu); + pr_err("failed to set up irq for cpu%d: %d\n", + cpu, ret); irq_dispose_mapping(cpu_to->clkevt.irq); cpu_to->clkevt.irq = 0; goto out_irq; @@ -317,11 +320,14 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) register_current_timer_delay(&tegra_delay_timer); - cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, - "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, - tegra_timer_stop); + ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, + tegra_timer_stop); + if (ret) + pr_err("failed to set up cpu hp state: %d\n", ret); return ret; + out_irq: for_each_possible_cpu(cpu) { struct timer_of *cpu_to; @@ -334,6 +340,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) } out: timer_of_cleanup(to); + return ret; } @@ -357,8 +364,6 @@ static int __init tegra20_init_rtc(struct device_node *np) if (ret) return ret; - clocksource_register_hz(&suspend_rtc_clocksource, 1000); - - return 0; + return clocksource_register_hz(&suspend_rtc_clocksource, 1000); } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); -- 2.21.0