From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, T_DKIMWL_WL_HIGH,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33A7DC04A6B for ; Wed, 8 May 2019 13:43:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 071CB214AF for ; Wed, 8 May 2019 13:43:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557323039; bh=OJmgP1E+mmtjTsf1WtejtNwHG6Y398f4yIiaqFrrEiI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=jWjvgw55Yrq73er4qaI80Tn7SwiBK0WurJ+oB91l8HsGX6AdEd8q3GaItzFs1OWSP /eFoUsXrbRb4buehSfMV5+DnMWkA0/btr0tDbtORjt3qO2kpMfKA4C1/y58l2D0AMT XlGijjVt2rxR+oPdjbz5VFvIa/TKhoNEX1bsvBoo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727778AbfEHNn6 (ORCPT ); Wed, 8 May 2019 09:43:58 -0400 Received: from mail.kernel.org ([198.145.29.99]:56536 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727488AbfEHNnx (ORCPT ); Wed, 8 May 2019 09:43:53 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2B762216B7; Wed, 8 May 2019 13:43:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557323033; bh=OJmgP1E+mmtjTsf1WtejtNwHG6Y398f4yIiaqFrrEiI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CdP1f7ILZqBPw2BMpB4qJDVKL+7JgHgaXfvD05pl9bLGdggralLbG1nqusElIuLzk +V4NFW49BWaHn0+jNsT3dT7A6EcCbx1yJHNdEHM1DR9ZK5EZO2KMnyVP2rZ9dIz0Zn GSMp1fayn7tbMI5icg6rWM+bxbIsWbmdYPpmY70U= From: Dinh Nguyen To: linux-mtd@lists.infradead.org Cc: dinguyen@kernel.org, marex@denx.de, tudor.ambarus@microchip.com, dwmw2@infradead.org, computersforpeace@gmail.com, bbrezillon@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Tien-Fong Chee Subject: [PATCHv4 2/2] mtd: spi-nor: cadence-quadspi: add reset control Date: Wed, 8 May 2019 08:43:38 -0500 Message-Id: <20190508134338.20565-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190508134338.20565-1-dinguyen@kernel.org> References: <20190508134338.20565-1-dinguyen@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Get the reset control properties for the QSPI controller and bring them out of reset. Most will have just one reset bit, but there is an additional OCP reset bit that is used ECC. The OCP reset bit will also need to get de-asserted as well. [1] [1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html Suggested-by: Tien-Fong Chee Signed-off-by: Dinh Nguyen --- v4: fix compile error v3: return full error by using PTR_ERR(rtsc) move reset control calls until after the clock enables use udelay(2) to be safe Add optional OCP(Open Core Protocol) reset signal v2: use devm_reset_control_get_optional_exclusive print an error message return -EPROBE_DEFER --- drivers/mtd/spi-nor/cadence-quadspi.c | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 792628750eec..d3906e5a1d44 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -1336,6 +1337,8 @@ static int cqspi_probe(struct platform_device *pdev) struct cqspi_st *cqspi; struct resource *res; struct resource *res_ahb; + struct reset_control *rstc; + struct reset_control *rstc_ocp; const struct cqspi_driver_platdata *ddata; int ret; int irq; @@ -1402,6 +1405,33 @@ static int cqspi_probe(struct platform_device *pdev) goto probe_clk_failed; } + /* Obtain QSPI reset control */ + rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); + if (IS_ERR(rstc)) { + dev_err(dev, "Cannot get QSPI reset.\n"); + if (PTR_ERR(rstc) == -EPROBE_DEFER) + return PTR_ERR(rstc); + } + + rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); + if (IS_ERR(rstc_ocp)) { + dev_err(dev, "Cannot get QSPI OCP reset.\n"); + if (PTR_ERR(rstc_ocp) == -EPROBE_DEFER) + return PTR_ERR(rstc_ocp); + } + + if (rstc) { + reset_control_assert(rstc); + udelay(2); + reset_control_deassert(rstc); + } + + if (rstc_ocp) { + reset_control_assert(rstc_ocp); + udelay(2); + reset_control_deassert(rstc_ocp); + } + cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); ddata = of_device_get_match_data(dev); if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) -- 2.20.0