[PATCH 1/3] perf parse-regs: Split parse_regs

[PATCH 1/3] perf parse-regs: Split parse_regs

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

The available registers for --int-regs and --user-regs may be different,
e.g. XMM registers.

Split parse_regs into two dedicated functions for --int-regs and
--user-regs respectively.

Modify the warning message. "--user-regs=?" should be applied to show
the available registers for --user-regs.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 tools/perf/builtin-record.c          |  4 ++--
 tools/perf/util/parse-regs-options.c | 19 ++++++++++++++++---
 tools/perf/util/parse-regs-options.h |  3 ++-
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
index 386e665..45172bb 100644
--- a/tools/perf/builtin-record.c
+++ b/tools/perf/builtin-record.c
@@ -2029,10 +2029,10 @@ static struct option __record_options[] = {
 		    "use per-thread mmaps"),
 	OPT_CALLBACK_OPTARG('I', "intr-regs", &record.opts.sample_intr_regs, NULL, "any register",
 		    "sample selected machine registers on interrupt,"
-		    " use '-I?' to list register names", parse_regs),
+		    " use '-I?' to list register names", parse_intr_regs),
 	OPT_CALLBACK_OPTARG(0, "user-regs", &record.opts.sample_user_regs, NULL, "any register",
 		    "sample selected machine registers on interrupt,"
-		    " use '-I?' to list register names", parse_regs),
+		    " use '--user-regs=?' to list register names", parse_user_regs),
 	OPT_BOOLEAN(0, "running-time", &record.opts.running_time,
 		    "Record running/enabled time of read (:S) events"),
 	OPT_CALLBACK('k', "clockid", &record.opts,
diff --git a/tools/perf/util/parse-regs-options.c b/tools/perf/util/parse-regs-options.c
index 9cb187a..b21617f 100644
--- a/tools/perf/util/parse-regs-options.c
+++ b/tools/perf/util/parse-regs-options.c
@@ -5,8 +5,8 @@
 #include <subcmd/parse-options.h>
 #include "util/parse-regs-options.h"
 
-int
-parse_regs(const struct option *opt, const char *str, int unset)
+static int
+__parse_regs(const struct option *opt, const char *str, int unset, bool intr)
 {
 	uint64_t *mode = (uint64_t *)opt->value;
 	const struct sample_reg *r;
@@ -48,7 +48,8 @@ parse_regs(const struct option *opt, const char *str, int unset)
 					break;
 			}
 			if (!r->name) {
-				ui__warning("Unknown register \"%s\", check man page or run \"perf record -I?\"\n", s);
+				ui__warning("Unknown register \"%s\", check man page or run \"perf record %s?\"\n",
+					    s, intr ? "-I" : "--user-regs=");
 				goto error;
 			}
 
@@ -69,3 +70,15 @@ parse_regs(const struct option *opt, const char *str, int unset)
 	free(os);
 	return ret;
 }
+
+int
+parse_user_regs(const struct option *opt, const char *str, int unset)
+{
+	return __parse_regs(opt, str, unset, false);
+}
+
+int
+parse_intr_regs(const struct option *opt, const char *str, int unset)
+{
+	return __parse_regs(opt, str, unset, true);
+}
diff --git a/tools/perf/util/parse-regs-options.h b/tools/perf/util/parse-regs-options.h
index cdefb1a..2b23d25 100644
--- a/tools/perf/util/parse-regs-options.h
+++ b/tools/perf/util/parse-regs-options.h
@@ -2,5 +2,6 @@
 #ifndef _PERF_PARSE_REGS_OPTIONS_H
 #define _PERF_PARSE_REGS_OPTIONS_H 1
 struct option;
-int parse_regs(const struct option *opt, const char *str, int unset);
+int parse_user_regs(const struct option *opt, const char *str, int unset);
+int parse_intr_regs(const struct option *opt, const char *str, int unset);
 #endif /* _PERF_PARSE_REGS_OPTIONS_H */
-- 
2.7.4

[PATCH 2/3] perf parse-regs: Add generic support for non-gprs

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

Some non general purpose registers, e.g. XMM, can be collected on some
platforms, e.g. X86 Icelake.

Add a weak function has_non_gprs_support() to check if the
kernel/hardware support non-gprs collection.
Add a weak function non_gprs_mask() to return non-gprs mask.

By default, the non-gprs collection is not support. Specific platforms
should implement their own non-gprs functions if they can collect
non-gprs.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 tools/perf/util/parse-regs-options.c | 10 +++++++++-
 tools/perf/util/perf_regs.c          | 10 ++++++++++
 tools/perf/util/perf_regs.h          |  2 ++
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/tools/perf/util/parse-regs-options.c b/tools/perf/util/parse-regs-options.c
index b21617f..2f90f31 100644
--- a/tools/perf/util/parse-regs-options.c
+++ b/tools/perf/util/parse-regs-options.c
@@ -12,6 +12,7 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
 	const struct sample_reg *r;
 	char *s, *os = NULL, *p;
 	int ret = -1;
+	bool has_non_gprs = has_non_gprs_support(intr);
 
 	if (unset)
 		return 0;
@@ -37,6 +38,8 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
 			if (!strcmp(s, "?")) {
 				fprintf(stderr, "available registers: ");
 				for (r = sample_reg_masks; r->name; r++) {
+					if (!has_non_gprs && (r->mask & ~PERF_REGS_MASK))
+						break;
 					fprintf(stderr, "%s ", r->name);
 				}
 				fputc('\n', stderr);
@@ -44,6 +47,8 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
 				return -1;
 			}
 			for (r = sample_reg_masks; r->name; r++) {
+				if (!has_non_gprs && (r->mask & ~PERF_REGS_MASK))
+					continue;
 				if (!strcasecmp(s, r->name))
 					break;
 			}
@@ -64,8 +69,11 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
 	ret = 0;
 
 	/* default to all possible regs */
-	if (*mode == 0)
+	if (*mode == 0) {
 		*mode = PERF_REGS_MASK;
+		if (has_non_gprs)
+			*mode |= non_gprs_mask(intr);
+	}
 error:
 	free(os);
 	return ret;
diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
index 2acfcc5..0d278b6 100644
--- a/tools/perf/util/perf_regs.c
+++ b/tools/perf/util/perf_regs.c
@@ -13,6 +13,16 @@ int __weak arch_sdt_arg_parse_op(char *old_op __maybe_unused,
 	return SDT_ARG_SKIP;
 }
 
+bool __weak has_non_gprs_support(bool intr __maybe_unused)
+{
+	return false;
+}
+
+u64 __weak non_gprs_mask(bool intr __maybe_unused)
+{
+	return 0;
+}
+
 #ifdef HAVE_PERF_REGS_SUPPORT
 int perf_reg_value(u64 *valp, struct regs_dump *regs, int id)
 {
diff --git a/tools/perf/util/perf_regs.h b/tools/perf/util/perf_regs.h
index 1a15a4b..983b4e6 100644
--- a/tools/perf/util/perf_regs.h
+++ b/tools/perf/util/perf_regs.h
@@ -23,6 +23,8 @@ enum {
 };
 
 int arch_sdt_arg_parse_op(char *old_op, char **new_op);
+bool has_non_gprs_support(bool intr);
+u64 non_gprs_mask(bool intr);
 
 #ifdef HAVE_PERF_REGS_SUPPORT
 #include <perf_regs.h>
-- 
2.7.4

Re: [PATCH 2/3] perf parse-regs: Add generic support for non-gprs

[Arnaldo Carvalho de Melo]

Em Tue, May 14, 2019 at 07:39:12AM -0700, kan.liang@linux.intel.com escreveu:
> From: Kan Liang <kan.liang@linux.intel.com>
> 
> Some non general purpose registers, e.g. XMM, can be collected on some
> platforms, e.g. X86 Icelake.
> 
> Add a weak function has_non_gprs_support() to check if the
> kernel/hardware support non-gprs collection.
> Add a weak function non_gprs_mask() to return non-gprs mask.
> 
> By default, the non-gprs collection is not support. Specific platforms
> should implement their own non-gprs functions if they can collect
> non-gprs.
> 
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> ---
>  tools/perf/util/parse-regs-options.c | 10 +++++++++-
>  tools/perf/util/perf_regs.c          | 10 ++++++++++
>  tools/perf/util/perf_regs.h          |  2 ++
>  3 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/perf/util/parse-regs-options.c b/tools/perf/util/parse-regs-options.c
> index b21617f..2f90f31 100644
> --- a/tools/perf/util/parse-regs-options.c
> +++ b/tools/perf/util/parse-regs-options.c
> @@ -12,6 +12,7 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
>  	const struct sample_reg *r;
>  	char *s, *os = NULL, *p;
>  	int ret = -1;
> +	bool has_non_gprs = has_non_gprs_support(intr);

This is generic code, what does "non gprs" means for !Intel? Can we come
up with a better, not architecture specific jargon? Or you mean "general
purpose registers"?

Perhaps we can ask for a register mask for use with intr? I.e.:

For the -I/--intr-regs

        uint64_t mask = arch__intr_reg_mask();

And for --user-regs

        uint64_t mask = arch__user_reg_mask();

And then on that loop do:

  	for (r = sample_reg_masks; r->name; r++) {
		if (r->mask & mask))
  			fprintf(stderr, "%s ", r->name);
  	}

?
  
>  	if (unset)
>  		return 0;
> @@ -37,6 +38,8 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
>  			if (!strcmp(s, "?")) {
>  				fprintf(stderr, "available registers: ");
>  				for (r = sample_reg_masks; r->name; r++) {
> +					if (!has_non_gprs && (r->mask & ~PERF_REGS_MASK))
> +						break;
>  					fprintf(stderr, "%s ", r->name);
>  				}
>  				fputc('\n', stderr);
> @@ -44,6 +47,8 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
>  				return -1;
>  			}
>  			for (r = sample_reg_masks; r->name; r++) {
> +				if (!has_non_gprs && (r->mask & ~PERF_REGS_MASK))
> +					continue;
>  				if (!strcasecmp(s, r->name))
>  					break;
>  			}
> @@ -64,8 +69,11 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
>  	ret = 0;
>  
>  	/* default to all possible regs */
> -	if (*mode == 0)
> +	if (*mode == 0) {
>  		*mode = PERF_REGS_MASK;
> +		if (has_non_gprs)
> +			*mode |= non_gprs_mask(intr);
> +	}
>  error:
>  	free(os);
>  	return ret;
> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
> index 2acfcc5..0d278b6 100644
> --- a/tools/perf/util/perf_regs.c
> +++ b/tools/perf/util/perf_regs.c
> @@ -13,6 +13,16 @@ int __weak arch_sdt_arg_parse_op(char *old_op __maybe_unused,
>  	return SDT_ARG_SKIP;
>  }
>  
> +bool __weak has_non_gprs_support(bool intr __maybe_unused)
> +{
> +	return false;
> +}
> +
> +u64 __weak non_gprs_mask(bool intr __maybe_unused)
> +{
> +	return 0;
> +}
> +
>  #ifdef HAVE_PERF_REGS_SUPPORT
>  int perf_reg_value(u64 *valp, struct regs_dump *regs, int id)
>  {
> diff --git a/tools/perf/util/perf_regs.h b/tools/perf/util/perf_regs.h
> index 1a15a4b..983b4e6 100644
> --- a/tools/perf/util/perf_regs.h
> +++ b/tools/perf/util/perf_regs.h
> @@ -23,6 +23,8 @@ enum {
>  };
>  
>  int arch_sdt_arg_parse_op(char *old_op, char **new_op);
> +bool has_non_gprs_support(bool intr);
> +u64 non_gprs_mask(bool intr);
>  
>  #ifdef HAVE_PERF_REGS_SUPPORT
>  #include <perf_regs.h>
> -- 
> 2.7.4

-- 

- Arnaldo

Re: [PATCH 2/3] perf parse-regs: Add generic support for non-gprs

[Liang, Kan]

On 5/14/2019 2:19 PM, Arnaldo Carvalho de Melo wrote:
> Em Tue, May 14, 2019 at 07:39:12AM -0700, kan.liang@linux.intel.com escreveu:
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> Some non general purpose registers, e.g. XMM, can be collected on some
>> platforms, e.g. X86 Icelake.
>>
>> Add a weak function has_non_gprs_support() to check if the
>> kernel/hardware support non-gprs collection.
>> Add a weak function non_gprs_mask() to return non-gprs mask.
>>
>> By default, the non-gprs collection is not support. Specific platforms
>> should implement their own non-gprs functions if they can collect
>> non-gprs.
>>
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>> ---
>>   tools/perf/util/parse-regs-options.c | 10 +++++++++-
>>   tools/perf/util/perf_regs.c          | 10 ++++++++++
>>   tools/perf/util/perf_regs.h          |  2 ++
>>   3 files changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/tools/perf/util/parse-regs-options.c b/tools/perf/util/parse-regs-options.c
>> index b21617f..2f90f31 100644
>> --- a/tools/perf/util/parse-regs-options.c
>> +++ b/tools/perf/util/parse-regs-options.c
>> @@ -12,6 +12,7 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
>>   	const struct sample_reg *r;
>>   	char *s, *os = NULL, *p;
>>   	int ret = -1;
>> +	bool has_non_gprs = has_non_gprs_support(intr);
> 
> This is generic code, what does "non gprs" means for !Intel? Can we come
> up with a better, not architecture specific jargon? Or you mean "general
> purpose registers"?

I mean "general purpose registers".

> 
> Perhaps we can ask for a register mask for use with intr? I.e.:
> 
> For the -I/--intr-regs
> 
>          uint64_t mask = arch__intr_reg_mask();
> 
> And for --user-regs
> 
>          uint64_t mask = arch__user_reg_mask();
> 
> And then on that loop do:
> 
>    	for (r = sample_reg_masks; r->name; r++) {
> 		if (r->mask & mask))
>    			fprintf(stderr, "%s ", r->name);
>    	}
> 
> ?

Yes, it looks like a little bit simpler than my implementation.
I will send out V2.

Thanks,
Kan

>    
>>   	if (unset)
>>   		return 0;
>> @@ -37,6 +38,8 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
>>   			if (!strcmp(s, "?")) {
>>   				fprintf(stderr, "available registers: ");
>>   				for (r = sample_reg_masks; r->name; r++) {
>> +					if (!has_non_gprs && (r->mask & ~PERF_REGS_MASK))
>> +						break;
>>   					fprintf(stderr, "%s ", r->name);
>>   				}
>>   				fputc('\n', stderr);
>> @@ -44,6 +47,8 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
>>   				return -1;
>>   			}
>>   			for (r = sample_reg_masks; r->name; r++) {
>> +				if (!has_non_gprs && (r->mask & ~PERF_REGS_MASK))
>> +					continue;
>>   				if (!strcasecmp(s, r->name))
>>   					break;
>>   			}
>> @@ -64,8 +69,11 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
>>   	ret = 0;
>>   
>>   	/* default to all possible regs */
>> -	if (*mode == 0)
>> +	if (*mode == 0) {
>>   		*mode = PERF_REGS_MASK;
>> +		if (has_non_gprs)
>> +			*mode |= non_gprs_mask(intr);
>> +	}
>>   error:
>>   	free(os);
>>   	return ret;
>> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
>> index 2acfcc5..0d278b6 100644
>> --- a/tools/perf/util/perf_regs.c
>> +++ b/tools/perf/util/perf_regs.c
>> @@ -13,6 +13,16 @@ int __weak arch_sdt_arg_parse_op(char *old_op __maybe_unused,
>>   	return SDT_ARG_SKIP;
>>   }
>>   
>> +bool __weak has_non_gprs_support(bool intr __maybe_unused)
>> +{
>> +	return false;
>> +}
>> +
>> +u64 __weak non_gprs_mask(bool intr __maybe_unused)
>> +{
>> +	return 0;
>> +}
>> +
>>   #ifdef HAVE_PERF_REGS_SUPPORT
>>   int perf_reg_value(u64 *valp, struct regs_dump *regs, int id)
>>   {
>> diff --git a/tools/perf/util/perf_regs.h b/tools/perf/util/perf_regs.h
>> index 1a15a4b..983b4e6 100644
>> --- a/tools/perf/util/perf_regs.h
>> +++ b/tools/perf/util/perf_regs.h
>> @@ -23,6 +23,8 @@ enum {
>>   };
>>   
>>   int arch_sdt_arg_parse_op(char *old_op, char **new_op);
>> +bool has_non_gprs_support(bool intr);
>> +u64 non_gprs_mask(bool intr);
>>   
>>   #ifdef HAVE_PERF_REGS_SUPPORT
>>   #include <perf_regs.h>
>> -- 
>> 2.7.4
> 

Re: [PATCH 2/3] perf parse-regs: Add generic support for non-gprs

[Arnaldo Carvalho de Melo]

Em Tue, May 14, 2019 at 03:25:51PM -0400, Liang, Kan escreveu:
> 
> 
> On 5/14/2019 2:19 PM, Arnaldo Carvalho de Melo wrote:
> > Em Tue, May 14, 2019 at 07:39:12AM -0700, kan.liang@linux.intel.com escreveu:
> > > From: Kan Liang <kan.liang@linux.intel.com>
> > > 
> > > Some non general purpose registers, e.g. XMM, can be collected on some
> > > platforms, e.g. X86 Icelake.
> > > 
> > > Add a weak function has_non_gprs_support() to check if the
> > > kernel/hardware support non-gprs collection.
> > > Add a weak function non_gprs_mask() to return non-gprs mask.
> > > 
> > > By default, the non-gprs collection is not support. Specific platforms
> > > should implement their own non-gprs functions if they can collect
> > > non-gprs.
> > > 
> > > Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> > > ---
> > >   tools/perf/util/parse-regs-options.c | 10 +++++++++-
> > >   tools/perf/util/perf_regs.c          | 10 ++++++++++
> > >   tools/perf/util/perf_regs.h          |  2 ++
> > >   3 files changed, 21 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/tools/perf/util/parse-regs-options.c b/tools/perf/util/parse-regs-options.c
> > > index b21617f..2f90f31 100644
> > > --- a/tools/perf/util/parse-regs-options.c
> > > +++ b/tools/perf/util/parse-regs-options.c
> > > @@ -12,6 +12,7 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
> > >   	const struct sample_reg *r;
> > >   	char *s, *os = NULL, *p;
> > >   	int ret = -1;
> > > +	bool has_non_gprs = has_non_gprs_support(intr);
> > 
> > This is generic code, what does "non gprs" means for !Intel? Can we come
> > up with a better, not architecture specific jargon? Or you mean "general
> > purpose registers"?
> 
> I mean "general purpose registers".

Ok
 
> > 
> > Perhaps we can ask for a register mask for use with intr? I.e.:
> > 
> > For the -I/--intr-regs
> > 
> >          uint64_t mask = arch__intr_reg_mask();
> > 
> > And for --user-regs
> > 
> >          uint64_t mask = arch__user_reg_mask();
> > 
> > And then on that loop do:
> > 
> >    	for (r = sample_reg_masks; r->name; r++) {
> > 		if (r->mask & mask))
> >    			fprintf(stderr, "%s ", r->name);
> >    	}
> > 
> > ?
> 
> Yes, it looks like a little bit simpler than my implementation.
> I will send out V2.

Thanks!
 
> Thanks,
> Kan
> 
> > >   	if (unset)
> > >   		return 0;
> > > @@ -37,6 +38,8 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
> > >   			if (!strcmp(s, "?")) {
> > >   				fprintf(stderr, "available registers: ");
> > >   				for (r = sample_reg_masks; r->name; r++) {
> > > +					if (!has_non_gprs && (r->mask & ~PERF_REGS_MASK))
> > > +						break;
> > >   					fprintf(stderr, "%s ", r->name);
> > >   				}
> > >   				fputc('\n', stderr);
> > > @@ -44,6 +47,8 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
> > >   				return -1;
> > >   			}
> > >   			for (r = sample_reg_masks; r->name; r++) {
> > > +				if (!has_non_gprs && (r->mask & ~PERF_REGS_MASK))
> > > +					continue;
> > >   				if (!strcasecmp(s, r->name))
> > >   					break;
> > >   			}
> > > @@ -64,8 +69,11 @@ __parse_regs(const struct option *opt, const char *str, int unset, bool intr)
> > >   	ret = 0;
> > >   	/* default to all possible regs */
> > > -	if (*mode == 0)
> > > +	if (*mode == 0) {
> > >   		*mode = PERF_REGS_MASK;
> > > +		if (has_non_gprs)
> > > +			*mode |= non_gprs_mask(intr);
> > > +	}
> > >   error:
> > >   	free(os);
> > >   	return ret;
> > > diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c
> > > index 2acfcc5..0d278b6 100644
> > > --- a/tools/perf/util/perf_regs.c
> > > +++ b/tools/perf/util/perf_regs.c
> > > @@ -13,6 +13,16 @@ int __weak arch_sdt_arg_parse_op(char *old_op __maybe_unused,
> > >   	return SDT_ARG_SKIP;
> > >   }
> > > +bool __weak has_non_gprs_support(bool intr __maybe_unused)
> > > +{
> > > +	return false;
> > > +}
> > > +
> > > +u64 __weak non_gprs_mask(bool intr __maybe_unused)
> > > +{
> > > +	return 0;
> > > +}
> > > +
> > >   #ifdef HAVE_PERF_REGS_SUPPORT
> > >   int perf_reg_value(u64 *valp, struct regs_dump *regs, int id)
> > >   {
> > > diff --git a/tools/perf/util/perf_regs.h b/tools/perf/util/perf_regs.h
> > > index 1a15a4b..983b4e6 100644
> > > --- a/tools/perf/util/perf_regs.h
> > > +++ b/tools/perf/util/perf_regs.h
> > > @@ -23,6 +23,8 @@ enum {
> > >   };
> > >   int arch_sdt_arg_parse_op(char *old_op, char **new_op);
> > > +bool has_non_gprs_support(bool intr);
> > > +u64 non_gprs_mask(bool intr);
> > >   #ifdef HAVE_PERF_REGS_SUPPORT
> > >   #include <perf_regs.h>
> > > -- 
> > > 2.7.4
> > 

-- 

- Arnaldo

[PATCH 3/3] perf regs x86: Add X86 support for non-gprs

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

XMM registers can be collected on Icelake and later platforms.

Add specific has_non_gprs_support(), which creating an event to check if
the kernel and hardware can collect XMM registers.

Add specific non_gprs_mask() to return the mask of XMM registers.

The XMM registers collection is only supported with --int-regs option.

Test on Skylake which doesn't support XMM registers collection. There is
nothing changed.

   #perf record -I?
   available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9
   R10 R11 R12 R13 R14 R15

   Usage: perf record [<options>] [<command>]
    or: perf record [<options>] -- <command> [<options>]

    -I, --intr-regs[=<any register>]
                          sample selected machine registers on
   interrupt, use '-I?' to list register names

   #perf record -I
   [ perf record: Woken up 1 times to write data ]
   [ perf record: Captured and wrote 0.905 MB perf.data (2520 samples) ]

   #perf evlist -v
   cycles: size: 112, { sample_period, sample_freq }: 4000, sample_type:
   IP|TID|TIME|CPU|PERIOD|REGS_INTR, read_format: ID, disabled: 1,
   inherit: 1, mmap: 1, comm: 1, freq: 1, task: 1, precise_ip: 3,
   sample_id_all: 1, exclude_guest: 1, mmap2: 1, comm_exec: 1, ksymbol:
   1, bpf_event: 1, sample_regs_intr: 0xff0fff

Test on Icelake which support XMM registers collection.

   #perf record -I?
   available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9 R10
   R11 R12 R13 R14 R15 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9
   XMM10 XMM11 XMM12 XMM13 XMM14 XMM15

   Usage: perf record [<options>] [<command>]
    or: perf record [<options>] -- <command> [<options>]

    -I, --intr-regs[=<any register>]
                          sample selected machine registers on
   interrupt, use '-I?' to list register names

   #perf record -I
   [ perf record: Woken up 1 times to write data ]
   [ perf record: Captured and wrote 0.800 MB perf.data (318 samples) ]

   #perf evlist -v
   cycles: size: 112, { sample_period, sample_freq }: 4000, sample_type:
   IP|TID|TIME|CPU|PERIOD|REGS_INTR, read_format: ID, disabled: 1,
   inherit: 1, mmap: 1, comm: 1, freq: 1, task: 1, precise_ip: 3,
   sample_id_all: 1, exclude_guest: 1, mmap2: 1, comm_exec: 1, ksymbol:
   1, bpf_event: 1, sample_regs_intr: 0xffffffff00ff0fff

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 tools/perf/arch/x86/include/perf_regs.h |  1 +
 tools/perf/arch/x86/util/perf_regs.c    | 36 +++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/tools/perf/arch/x86/include/perf_regs.h b/tools/perf/arch/x86/include/perf_regs.h
index b732133..b7cd91a 100644
--- a/tools/perf/arch/x86/include/perf_regs.h
+++ b/tools/perf/arch/x86/include/perf_regs.h
@@ -9,6 +9,7 @@
 void perf_regs_load(u64 *regs);
 
 #define PERF_REGS_MAX PERF_REG_X86_XMM_MAX
+#define PERF_XMM_REGS_MASK	(~((1ULL << PERF_REG_X86_XMM0) - 1))
 #ifndef HAVE_ARCH_X86_64_SUPPORT
 #define PERF_REGS_MASK ((1ULL << PERF_REG_X86_32_MAX) - 1)
 #define PERF_SAMPLE_REGS_ABI PERF_SAMPLE_REGS_ABI_32
diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/util/perf_regs.c
index 71d7604..963b126 100644
--- a/tools/perf/arch/x86/util/perf_regs.c
+++ b/tools/perf/arch/x86/util/perf_regs.c
@@ -270,3 +270,39 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op)
 
 	return SDT_ARG_VALID;
 }
+
+bool has_non_gprs_support(bool intr)
+{
+	struct perf_event_attr attr = {
+		.type			= PERF_TYPE_HARDWARE,
+		.config			= PERF_COUNT_HW_CPU_CYCLES,
+		.sample_period		= 1,
+		.sample_type		= PERF_SAMPLE_REGS_INTR,
+		.sample_regs_intr	= PERF_XMM_REGS_MASK,
+		.precise_ip		= 1,
+		.disabled 		= 1,
+		.exclude_kernel		= 1,
+	};
+	int fd;
+
+	if (!intr)
+		return false;
+
+	event_attr_init(&attr);
+
+	fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
+	if (fd != -1) {
+		close(fd);
+		return true;
+	}
+
+	return false;
+}
+
+u64 non_gprs_mask(bool intr)
+{
+	if (intr)
+		return PERF_XMM_REGS_MASK;
+
+	return 0;
+}
-- 
2.7.4