* [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72
@ 2019-05-13 20:25 Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Florian Fainelli @ 2019-05-13 20:25 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
Namhyung Kim, Will Deacon, Mark Rutland, Catalin Marinas,
moderated list:ARM PMU PROFILING AND DEBUGGING, John Garry,
Ganapatrao Kulkarni, Sean V Kelley
Hi all,
Based on discussion about the last patch, it turned out that we can
remove the [[:xdigit:]] wildcard entirely since get_cpuid_str() strips
the revision bits anyway.
Florian Fainelli (3):
perf vendor events arm64: Remove [[:xdigit:]] wildcard
perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events
perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
.../arm/cortex-a57-a72/core-imp-def.json | 179 ++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 5 +-
2 files changed, 183 insertions(+), 1 deletion(-)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
@ 2019-05-13 20:25 ` Florian Fainelli
2019-05-15 9:02 ` John Garry
2019-05-18 9:28 ` [tip:perf/core] " tip-bot for Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events Florian Fainelli
` (2 subsequent siblings)
3 siblings, 2 replies; 9+ messages in thread
From: Florian Fainelli @ 2019-05-13 20:25 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
Namhyung Kim, Will Deacon, Mark Rutland, Catalin Marinas,
moderated list:ARM PMU PROFILING AND DEBUGGING, John Garry,
Ganapatrao Kulkarni, Sean V Kelley
ARM64's implementation of get_cpuidr_str() masks out the revision bits
[3:0] while reading the CPU identifier, there is no need for the
[[:xdigit:]] wildcard.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 59cd8604b0bd..da5ff2204bf6 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,7 +12,7 @@
#
#
#Family-model,Version,Filename,EventType
-0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
+0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
@ 2019-05-13 20:25 ` Florian Fainelli
2019-05-18 9:29 ` [tip:perf/core] " tip-bot for Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
2019-05-15 19:13 ` [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Arnaldo Carvalho de Melo
3 siblings, 1 reply; 9+ messages in thread
From: Florian Fainelli @ 2019-05-13 20:25 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Alexander Shishkin, Catalin Marinas, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra,
bcm-kernel-feedback-list, linux-arm-kernel,
Arnaldo Carvalho de Melo, Ingo Molnar, Arnaldo Carvalho de Melo,
Will Deacon, John Garry, Ganapatrao Kulkarni, Sean V Kelley
Broadcom's Brahma-B53 CPUs support the same type of events that the
Cortex-A53 supports, recognize its CPUID and map it to the cortex-a53
events.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging)
Link: http://lkml.kernel.org/r/20190405165047.15847-1-f.fainelli@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index da5ff2204bf6..013155f1eb58 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -13,6 +13,7 @@
#
#Family-model,Version,Filename,EventType
0x00000000410fd030,v1,arm/cortex-a53,core
+0x00000000420f1000,v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events Florian Fainelli
@ 2019-05-13 20:25 ` Florian Fainelli
2019-05-18 9:30 ` [tip:perf/core] " tip-bot for Florian Fainelli
2019-05-15 19:13 ` [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Arnaldo Carvalho de Melo
3 siblings, 1 reply; 9+ messages in thread
From: Florian Fainelli @ 2019-05-13 20:25 UTC (permalink / raw)
To: linux-kernel
Cc: Florian Fainelli, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
Namhyung Kim, Will Deacon, Mark Rutland, Catalin Marinas,
moderated list:ARM PMU PROFILING AND DEBUGGING, John Garry,
Ganapatrao Kulkarni, Sean V Kelley
The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
up to the RC_ST_SPEC (0x91) event with the exception of:
- L1D_CACHE_REFILL_INNER (0x44)
- L1D_CACHE_REFILL_OUTER (0x45)
- L1D_TLB_RD (0x4E)
- L1D_TLB_WR (0x4F)
- L2D_TLB_REFILL_RD (0x5C)
- L2D_TLB_REFILL_WR (0x5D)
- L2D_TLB_RD (0x5E)
- L2D_TLB_WR (0x5F)
- STREX_SPEC (0x6F)
Create an appropriate JSON file for mapping those events and update the
mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
file.
Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../arm/cortex-a57-a72/core-imp-def.json | 179 ++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +
2 files changed, 181 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
new file mode 100644
index 000000000000..0ac9b7927450
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
@@ -0,0 +1,179 @@
+[
+ {
+ "ArchStdEvent": "L1D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NORMAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_PERIPH",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC",
+ },
+ {
+ "ArchStdEvent": "LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "DP_SPEC",
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC",
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC",
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC",
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC",
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF",
+ },
+ {
+ "ArchStdEvent": "EXC_SVC",
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ",
+ },
+ {
+ "ArchStdEvent": "EXC_SMC",
+ },
+ {
+ "ArchStdEvent": "EXC_HVC",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ",
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 013155f1eb58..927fcddcb4aa 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -14,6 +14,8 @@
#Family-model,Version,Filename,EventType
0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f1000,v1,arm/cortex-a53,core
+0x00000000410fd070,v1,arm/cortex-a57-a72,core
+0x00000000410fd080,v1,arm/cortex-a57-a72,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
@ 2019-05-15 9:02 ` John Garry
2019-05-18 9:28 ` [tip:perf/core] " tip-bot for Florian Fainelli
1 sibling, 0 replies; 9+ messages in thread
From: John Garry @ 2019-05-15 9:02 UTC (permalink / raw)
To: Florian Fainelli, linux-kernel
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, Will Deacon,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
Ganapatrao Kulkarni, Namhyung Kim, Sean V Kelley, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On 13/05/2019 21:25, Florian Fainelli wrote:
> ARM64's implementation of get_cpuidr_str() masks out the revision bits
> [3:0] while reading the CPU identifier, there is no need for the
> [[:xdigit:]] wildcard.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> index 59cd8604b0bd..da5ff2204bf6 100644
> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> @@ -12,7 +12,7 @@
> #
JFYI, this was discussed before, but this a53 entry seemed to make it
though:
https://lkml.org/lkml/2018/3/7/1236
> #
> #Family-model,Version,Filename,EventType
> -0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
> +0x00000000410fd030,v1,arm/cortex-a53,core
> 0x00000000420f5160,v1,cavium/thunderx2,core
> 0x00000000430f0af0,v1,cavium/thunderx2,core
> 0x00000000480fd010,v1,hisilicon/hip08,core
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
` (2 preceding siblings ...)
2019-05-13 20:25 ` [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
@ 2019-05-15 19:13 ` Arnaldo Carvalho de Melo
3 siblings, 0 replies; 9+ messages in thread
From: Arnaldo Carvalho de Melo @ 2019-05-15 19:13 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-kernel, Peter Zijlstra, Ingo Molnar, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Will Deacon, Mark Rutland,
Catalin Marinas, moderated list:ARM PMU PROFILING AND DEBUGGING,
John Garry, Ganapatrao Kulkarni, Sean V Kelley
Em Mon, May 13, 2019 at 01:25:19PM -0700, Florian Fainelli escreveu:
> Hi all,
>
> Based on discussion about the last patch, it turned out that we can
> remove the [[:xdigit:]] wildcard entirely since get_cpuid_str() strips
> the revision bits anyway.
Thanks, applied.
- Arnaldo
^ permalink raw reply [flat|nested] 9+ messages in thread
* [tip:perf/core] perf vendor events arm64: Remove [[:xdigit:]] wildcard
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
2019-05-15 9:02 ` John Garry
@ 2019-05-18 9:28 ` tip-bot for Florian Fainelli
1 sibling, 0 replies; 9+ messages in thread
From: tip-bot for Florian Fainelli @ 2019-05-18 9:28 UTC (permalink / raw)
To: linux-tip-commits
Cc: catalin.marinas, linux-kernel, mark.rutland, f.fainelli,
alexander.shishkin, jolsa, peterz, hpa, ganapatrao.kulkarni,
will.deacon, acme, mingo, tglx, seanvk.dev, namhyung, john.garry
Commit-ID: ae833a6124b1bfe98bea428da86fe5b83b5785a7
Gitweb: https://git.kernel.org/tip/ae833a6124b1bfe98bea428da86fe5b83b5785a7
Author: Florian Fainelli <f.fainelli@gmail.com>
AuthorDate: Mon, 13 May 2019 13:25:20 -0700
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Wed, 15 May 2019 16:36:49 -0300
perf vendor events arm64: Remove [[:xdigit:]] wildcard
ARM64's implementation of get_cpuidr_str() masks out the revision bits
[3:0] while reading the CPU identifier, there is no need for the
[[:xdigit:]] wildcard.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sean V Kelley <seanvk.dev@oregontracks.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging)
Link: http://lkml.kernel.org/r/20190513202522.9050-2-f.fainelli@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 59cd8604b0bd..da5ff2204bf6 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,7 +12,7 @@
#
#
#Family-model,Version,Filename,EventType
-0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
+0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip:perf/core] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events
2019-05-13 20:25 ` [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events Florian Fainelli
@ 2019-05-18 9:29 ` tip-bot for Florian Fainelli
0 siblings, 0 replies; 9+ messages in thread
From: tip-bot for Florian Fainelli @ 2019-05-18 9:29 UTC (permalink / raw)
To: linux-tip-commits
Cc: seanvk.dev, hpa, alexander.shishkin, namhyung, f.fainelli,
will.deacon, tglx, linux-kernel, mingo, ganapatrao.kulkarni,
mark.rutland, john.garry, jolsa, acme, catalin.marinas, peterz
Commit-ID: 93fe8f1e11042e6cdf6f36f4e8ac111c7b818fc7
Gitweb: https://git.kernel.org/tip/93fe8f1e11042e6cdf6f36f4e8ac111c7b818fc7
Author: Florian Fainelli <f.fainelli@gmail.com>
AuthorDate: Mon, 13 May 2019 13:25:21 -0700
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Wed, 15 May 2019 16:36:49 -0300
perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events
Broadcom's Brahma-B53 CPUs support the same type of events that the
Cortex-A53 supports, recognize its CPUID and map it to the cortex-a53
events.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sean V Kelley <seanvk.dev@oregontracks.org>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org (moderated list
Link: http://lkml.kernel.org/r/20190513202522.9050-3-f.fainelli@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index da5ff2204bf6..013155f1eb58 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -13,6 +13,7 @@
#
#Family-model,Version,Filename,EventType
0x00000000410fd030,v1,arm/cortex-a53,core
+0x00000000420f1000,v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip:perf/core] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
2019-05-13 20:25 ` [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
@ 2019-05-18 9:30 ` tip-bot for Florian Fainelli
0 siblings, 0 replies; 9+ messages in thread
From: tip-bot for Florian Fainelli @ 2019-05-18 9:30 UTC (permalink / raw)
To: linux-tip-commits
Cc: acme, tglx, mark.rutland, john.garry, ganapatrao.kulkarni,
alexander.shishkin, hpa, catalin.marinas, linux-kernel, jolsa,
mingo, seanvk.dev, will.deacon, namhyung, peterz, f.fainelli
Commit-ID: 7025fdbea3a67c5980b94574b755a5fd65ea8a36
Gitweb: https://git.kernel.org/tip/7025fdbea3a67c5980b94574b755a5fd65ea8a36
Author: Florian Fainelli <f.fainelli@gmail.com>
AuthorDate: Mon, 13 May 2019 13:25:22 -0700
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Wed, 15 May 2019 16:36:49 -0300
perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
up to the RC_ST_SPEC (0x91) event with the exception of:
- L1D_CACHE_REFILL_INNER (0x44)
- L1D_CACHE_REFILL_OUTER (0x45)
- L1D_TLB_RD (0x4E)
- L1D_TLB_WR (0x4F)
- L2D_TLB_REFILL_RD (0x5C)
- L2D_TLB_REFILL_WR (0x5D)
- L2D_TLB_RD (0x5E)
- L2D_TLB_WR (0x5F)
- STREX_SPEC (0x6F)
Create an appropriate JSON file for mapping those events and update the
mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
file.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: John Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sean V Kelley <seanvk.dev@oregontracks.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging)
Link: http://lkml.kernel.org/r/20190513202522.9050-4-f.fainelli@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../cortex-a57-a72}/core-imp-def.json | 92 +++++++++++++++++++---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +
2 files changed, 81 insertions(+), 13 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
similarity index 52%
copy from tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
copy to tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
index 752e47eb6977..0ac9b7927450 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
@@ -11,12 +11,6 @@
{
"ArchStdEvent": "L1D_CACHE_REFILL_WR",
},
- {
- "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
- },
- {
- "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
- },
{
"ArchStdEvent": "L1D_CACHE_WB_VICTIM",
},
@@ -33,22 +27,25 @@
"ArchStdEvent": "L1D_TLB_REFILL_WR",
},
{
- "ArchStdEvent": "L1D_TLB_RD",
+ "ArchStdEvent": "L2D_CACHE_RD",
},
{
- "ArchStdEvent": "L1D_TLB_WR",
+ "ArchStdEvent": "L2D_CACHE_WR",
},
{
- "ArchStdEvent": "L2D_TLB_REFILL_RD",
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
},
{
- "ArchStdEvent": "L2D_TLB_REFILL_WR",
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
},
{
- "ArchStdEvent": "L2D_TLB_RD",
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
},
{
- "ArchStdEvent": "L2D_TLB_WR",
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
},
{
"ArchStdEvent": "BUS_ACCESS_RD",
@@ -56,6 +53,18 @@
{
"ArchStdEvent": "BUS_ACCESS_WR",
},
+ {
+ "ArchStdEvent": "BUS_ACCESS_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NORMAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_PERIPH",
+ },
{
"ArchStdEvent": "MEM_ACCESS_RD",
},
@@ -71,6 +80,57 @@
{
"ArchStdEvent": "UNALIGNED_LDST_SPEC",
},
+ {
+ "ArchStdEvent": "LDREX_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC",
+ },
+ {
+ "ArchStdEvent": "LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "DP_SPEC",
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC",
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC",
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC",
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC",
+ },
{
"ArchStdEvent": "EXC_UNDEF",
},
@@ -109,5 +169,11 @@
},
{
"ArchStdEvent": "EXC_TRAP_FIQ",
- }
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC",
+ },
]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 013155f1eb58..927fcddcb4aa 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -14,6 +14,8 @@
#Family-model,Version,Filename,EventType
0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f1000,v1,arm/cortex-a53,core
+0x00000000410fd070,v1,arm/cortex-a57-a72,core
+0x00000000410fd080,v1,arm/cortex-a57-a72,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-05-18 9:30 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
2019-05-15 9:02 ` John Garry
2019-05-18 9:28 ` [tip:perf/core] " tip-bot for Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events Florian Fainelli
2019-05-18 9:29 ` [tip:perf/core] " tip-bot for Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
2019-05-18 9:30 ` [tip:perf/core] " tip-bot for Florian Fainelli
2019-05-15 19:13 ` [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Arnaldo Carvalho de Melo
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