From: Peter Zijlstra <peterz@infradead.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Raphael Gault <raphael.gault@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, mingo@redhat.com,
catalin.marinas@arm.com, will.deacon@arm.com, acme@kernel.org
Subject: Re: [PATCH 4/6] arm64: pmu: Add hook to handle pmu-related undefined instructions
Date: Fri, 17 May 2019 10:26:55 +0200 [thread overview]
Message-ID: <20190517082655.GK2623@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20190517080419.dziz4iqc7t4mpoej@blommer>
On Fri, May 17, 2019 at 09:04:20AM +0100, Mark Rutland wrote:
> Remember that this is in an undefined (trap) handler.
>
> If userspace _attempts_ to write to the registers, the CPU will trap to the
> kernel. The comment is perhaps misleading; when we "do nothing", the common
> trap handling code will send a SIGILL to userspace.
>
> It would probably be better to say something like:
>
> /*
> * If userspace is tries to read a counter that doesn't exist on this
> * CPU, we emulate it as reading as zero. This happens if userspace is
> * preempted between reading the idx and actually reading the counter,
> * and the seqlock and idx have already changed, so it's as-if the
> * counter has been reprogrammed with a different event.
Might be good to mention that userspace will/should discard the value it
reads, and therefore any value is good (including 0).
> * We don't permit userspace to write to these registers, and will
> * inject a SIGILL.
> */
>
> There is one caveat: userspace can write to PMSELR without trapping, so we will
> have to context-switch with the task. That only affects indirect addressing of
> PMU registers, and doesn't have a functional effect on the behaviour of the
> PMU, so that's benign from the PoV of perf.
Sad though; ideally you'd state that indirect addressing is
out-of-bounds and they get to keep the pieces. But I suspect you're
right that people will do it anyway and complain once it comes apart.
next prev parent reply other threads:[~2019-05-17 8:27 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-16 13:21 [RFC 0/6] arm64: Enable access to pmu registers by user-space Raphael Gault
2019-05-16 13:21 ` [PATCH 1/6] perf: arm64: Compile tests unconditionally Raphael Gault
2019-05-16 13:21 ` [PATCH 2/6] perf: arm64: Add test to check userspace access to hardware counters Raphael Gault
2019-05-16 13:21 ` [PATCH 3/6] arm64: pmu: Add function implementation to update event index in userpage Raphael Gault
2019-05-17 13:21 ` Mark Rutland
2019-05-16 13:21 ` [PATCH 4/6] arm64: pmu: Add hook to handle pmu-related undefined instructions Raphael Gault
2019-05-17 7:10 ` Peter Zijlstra
2019-05-17 7:35 ` Raphael Gault
2019-05-17 8:04 ` Mark Rutland
2019-05-17 8:26 ` Peter Zijlstra [this message]
2019-05-17 9:07 ` Peter Zijlstra
2019-05-16 13:21 ` [PATCH 5/6] arm64: perf: Enable pmu counter direct access for perf event on armv8 Raphael Gault
2019-05-16 13:21 ` [PATCH 6/6] Documentation: arm64: Document PMU counters access from userspace Raphael Gault
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