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[46.139.12.213]) by smtp.gmail.com with ESMTPSA id l14sm18337076wrt.57.2019.05.21.01.26.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 01:26:13 -0700 (PDT) Date: Tue, 21 May 2019 10:26:11 +0200 From: Ingo Molnar To: Stephane Eranian Cc: linux-kernel@vger.kernel.org, peterz@infradead.org, ak@linux.intel.com, kan.liang@intel.com, jolsa@redhat.com, vincent.weaver@maine.edu Subject: Re: [PATCH v2] perf/x86/intel/ds: fix EVENT vs. UEVENT PEBS constraints Message-ID: <20190521082611.GA34626@gmail.com> References: <20190521005246.423-1-eranian@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190521005246.423-1-eranian@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Stephane Eranian wrote: > This patch fixes an issue revealed by the following commit: > Commit 6b89d4c1ae85 ("perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking") > > That patch modified INTEL_FLAGS_EVENT_CONSTRAINT() to only look at the event code > when matching a constraint. If code+umask were needed, then the > INTEL_FLAGS_UEVENT_CONSTRAINT() macro was needed instead. > This broke with some of the constraints for PEBS events. > Several of them, including the one used for cycles:p, cycles:pp, cycles:ppp > fell in that category and caused the event to be rejected in PEBS mode. > In other words, on some platforms a cmdline such as: > > $ perf top -e cycles:pp > > would fail with EINVAL. > > This patch fixes this issue by properly using INTEL_FLAGS_UEVENT_CONSTRAINT() > when needed in the PEBS constraint tables. > > In v2: > - add fixes for Core2, Nehalem, Silvermont, and Atom > > Reported-by: Ingo Molnar > Signed-off-by: Stephane Eranian > --- > arch/x86/events/intel/ds.c | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) Thanks Stephane for the quick fixes! Ingo