From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40B11C28CC0 for ; Wed, 29 May 2019 10:30:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1A0D220B1F for ; Wed, 29 May 2019 10:30:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="XQxR27+W" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726761AbfE2Kad (ORCPT ); Wed, 29 May 2019 06:30:33 -0400 Received: from merlin.infradead.org ([205.233.59.134]:33956 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725990AbfE2Kad (ORCPT ); Wed, 29 May 2019 06:30:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=1dAPKEgrdA77wQkAtd5gC6oh+a8AzS+LHB60Y9C2ymk=; b=XQxR27+WnVTmp5Ulgy4i5STtT Tah9eldsP7kIUyYVcFMpcV2yfiLUNrTuxq7NrctEBZY/BTA5VkVO0y3AG0JU1L7l3DIUdZ0uGqe+W HGj2dMWylU+fuC3tbzcuTHkxanPs5RpoOrF0KRZyUwXHA1i3y/6asMWyvb9MPjfDtrLeTYdRgat96 PV++Vrl5gIlZyVldbQpRWiv71ourwwNj2fyMFURDzRnQUjQ3RXsab5FDy3brTD6QFF79shi3VMh5D IXzqdS1f8pqvORPrdrbvVa7LdmBiFmkwRPBPKWrz/uvWtx/hb5UMphU2JrU2FaVKbJ6TWE2pB8A7H alLHgBeWw==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=hirez.programming.kicks-ass.net) by merlin.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1hVvqV-0003TW-Mw; Wed, 29 May 2019 10:30:12 +0000 Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 45FBD201A7E6D; Wed, 29 May 2019 12:30:10 +0200 (CEST) Date: Wed, 29 May 2019 12:30:10 +0200 From: Peter Zijlstra To: Marco Elver Cc: Dmitry Vyukov , Mark Rutland , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Jonathan Corbet , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , the arch/x86 maintainers , Arnd Bergmann , Josh Poimboeuf , "open list:DOCUMENTATION" , LKML , linux-arch , kasan-dev Subject: Re: [PATCH 3/3] asm-generic, x86: Add bitops instrumentation for KASAN Message-ID: <20190529103010.GP2623@hirez.programming.kicks-ass.net> References: <20190528163258.260144-1-elver@google.com> <20190528163258.260144-3-elver@google.com> <20190528165036.GC28492@lakrids.cambridge.arm.com> <20190529100116.GM2623@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 29, 2019 at 12:16:31PM +0200, Marco Elver wrote: > On Wed, 29 May 2019 at 12:01, Peter Zijlstra wrote: > > > > On Wed, May 29, 2019 at 11:20:17AM +0200, Marco Elver wrote: > > > For the default, we decided to err on the conservative side for now, > > > since it seems that e.g. x86 operates only on the byte the bit is on. > > > > This is not correct, see for instance set_bit(): > > > > static __always_inline void > > set_bit(long nr, volatile unsigned long *addr) > > { > > if (IS_IMMEDIATE(nr)) { > > asm volatile(LOCK_PREFIX "orb %1,%0" > > : CONST_MASK_ADDR(nr, addr) > > : "iq" ((u8)CONST_MASK(nr)) > > : "memory"); > > } else { > > asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0" > > : : RLONG_ADDR(addr), "Ir" (nr) : "memory"); > > } > > } > > > > That results in: > > > > LOCK BTSQ nr, (addr) > > > > when @nr is not an immediate. > > Thanks for the clarification. Given that arm64 already instruments > bitops access to whole words, and x86 may also do so for some bitops, > it seems fine to instrument word-sized accesses by default. Is that > reasonable? Eminently -- the API is defined such; for bonus points KASAN should also do alignment checks on atomic ops. Future hardware will #AC on unaligned [*] LOCK prefix instructions. (*) not entirely accurate, it will only trap when crossing a line. https://lkml.kernel.org/r/1556134382-58814-1-git-send-email-fenghua.yu@intel.com