From: Kees Cook <keescook@chromium.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
x86@kernel.org, Peter Zijlstra <peterz@infradead.org>,
Dave Hansen <dave.hansen@intel.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] x86/asm: Pin sensitive CR4 bits
Date: Wed, 5 Jun 2019 07:28:52 -0700 [thread overview]
Message-ID: <201906050728.89B4834@keescook> (raw)
In-Reply-To: <20190604234422.29391-2-keescook@chromium.org>
On Tue, Jun 04, 2019 at 04:44:21PM -0700, Kees Cook wrote:
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 2c57fffebf9b..6b210be12734 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -366,6 +366,23 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c)
> cr4_clear_bits(X86_CR4_UMIP);
> }
>
> +DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
> +unsigned long cr4_pinned_bits __ro_after_init;
I missed EXPORT_SYMBOL()s for these -- I will fix in v3.
--
Kees Cook
next prev parent reply other threads:[~2019-06-05 14:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-04 23:44 [PATCH v2 0/2] x86/asm: Pin sensitive CR4 and CR0 bits Kees Cook
2019-06-04 23:44 ` [PATCH v2 1/2] x86/asm: Pin sensitive CR4 bits Kees Cook
2019-06-05 14:28 ` Kees Cook [this message]
2019-06-14 14:57 ` Thomas Gleixner
2019-06-15 3:19 ` Kees Cook
2019-06-16 22:26 ` Thomas Gleixner
2019-06-18 4:09 ` Kees Cook
2019-06-04 23:44 ` [PATCH v2 2/2] x86/asm: Pin sensitive CR0 bits Kees Cook
2019-06-14 14:58 ` Thomas Gleixner
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