From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,T_DKIMWL_WL_HIGH,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A28DDC28CC5 for ; Sat, 8 Jun 2019 11:43:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6FBC321530 for ; Sat, 8 Jun 2019 11:43:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559994192; bh=Xu0+t3OhrCS1y2hn65l4oChxMZzBDiH0Hf5geJGUV18=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=zSep4GcwPlRZ0vX6FqPJZmR1XCrOH5oo7hq6aWYgnb0QuLtP1ENqhoci0rIxK7kkX npS+9YLxcXo3ZpS3/YoNGGXyVW+YnXVJ5VFO4caz58sR1GRYXaFj2zJI/CO1fjgqVD iCmzoA5tAIO4Kqz11FvF3yfjBAuGsJ7bl5XHgdPA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728653AbfFHLnL (ORCPT ); Sat, 8 Jun 2019 07:43:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:60322 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728105AbfFHLnF (ORCPT ); Sat, 8 Jun 2019 07:43:05 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D39D7214D8; Sat, 8 Jun 2019 11:43:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559994184; bh=Xu0+t3OhrCS1y2hn65l4oChxMZzBDiH0Hf5geJGUV18=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t69oJ4QFXNgyqJyixxZR+ObNsjdROR4B+Q6aMZlpZgdsCkYvKpwvNi6aKrYeA3Edq hl/4DHRjPcscqBtJxpLmkg5pcjjofN4W6alR8N5qbjhIWKwYdXTop85KLts4iqZiez kxLhZq9kRv/xwDVGiCAMpjCRvPxr/C3gO4W//+BE= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Tony Lindgren , Stephen Boyd , Sasha Levin , linux-omap@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH AUTOSEL 4.19 08/49] clk: ti: clkctrl: Fix clkdm_clk handling Date: Sat, 8 Jun 2019 07:41:49 -0400 Message-Id: <20190608114232.8731-8-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190608114232.8731-1-sashal@kernel.org> References: <20190608114232.8731-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tony Lindgren [ Upstream commit 1cc54078d104f5b4d7e9f8d55362efa5a8daffdb ] We need to always call clkdm_clk_enable() and clkdm_clk_disable() even the clkctrl clock(s) enabled for the domain do not have any gate register bits. Otherwise clockdomains may never get enabled except when devices get probed with the legacy "ti,hwmods" devicetree property. Fixes: 88a172526c32 ("clk: ti: add support for clkctrl clocks") Signed-off-by: Tony Lindgren Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/ti/clkctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 421b05392220..ca3218337fd7 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -137,9 +137,6 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) int ret; union omap4_timeout timeout = { 0 }; - if (!clk->enable_bit) - return 0; - if (clk->clkdm) { ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); if (ret) { @@ -151,6 +148,9 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) } } + if (!clk->enable_bit) + return 0; + val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); val &= ~OMAP4_MODULEMODE_MASK; @@ -179,7 +179,7 @@ static void _omap4_clkctrl_clk_disable(struct clk_hw *hw) union omap4_timeout timeout = { 0 }; if (!clk->enable_bit) - return; + goto exit; val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); -- 2.20.1