From: Peter Zijlstra <peterz@infradead.org>
To: Alan Stern <stern@rowland.harvard.edu>
Cc: David Howells <dhowells@redhat.com>,
akiyks@gmail.com, andrea.parri@amarulasolutions.com,
boqun.feng@gmail.com, dlustig@nvidia.com, j.alglave@ucl.ac.uk,
luc.maranget@inria.fr, npiggin@gmail.com, paulmck@linux.ibm.com,
will.deacon@arm.com, paul.burton@mips.com,
linux-kernel@vger.kernel.org, torvalds@linux-foundation.org
Subject: Re: [PATCH v2 0/4] atomic: Fixes to smp_mb__{before,after}_atomic() and mips.
Date: Thu, 13 Jun 2019 20:00:29 +0200 [thread overview]
Message-ID: <20190613180029.GO3436@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <Pine.LNX.4.44L0.1906131253230.1307-100000@iolanthe.rowland.org>
On Thu, Jun 13, 2019 at 12:58:11PM -0400, Alan Stern wrote:
> On Thu, 13 Jun 2019, David Howells wrote:
>
> > Peter Zijlstra <peterz@infradead.org> wrote:
> >
> > > Basically we fail for:
> > >
> > > *x = 1;
> > > atomic_inc(u);
> > > smp_mb__after_atomic();
> > > r0 = *y;
> > >
> > > Because, while the atomic_inc() implies memory order, it
> > > (surprisingly) does not provide a compiler barrier. This then allows
> > > the compiler to re-order like so:
> >
> > To quote memory-barriers.txt:
> >
> > (*) smp_mb__before_atomic();
> > (*) smp_mb__after_atomic();
> >
> > These are for use with atomic (such as add, subtract, increment and
> > decrement) functions that don't return a value, especially when used for
> > reference counting. These functions do not imply memory barriers.
> >
> > so it's entirely to be expected?
>
> The text is perhaps ambiguous. It means that the atomic functions
> which don't return values -- like atomic_inc() -- do not imply memory
> barriers. It doesn't mean that smp_mb__before_atomic() and
> smp_mb__after_atomic() do not imply memory barriers.
>
> The behavior Peter described is not to be expected. The expectation is
> that the smp_mb__after_atomic() in the example should force the "*x =
> 1" store to execute before the "r0 = *y" load. But on current x86 it
> doesn't force this, for the reason explained in the description.
Indeed, thanks Alan.
The other other approach would be to upgrade smp_mb__{before,after}_mb()
to actual full memory barriers on x86, but that seems quite rediculous
since atomic_inc() already does all the expensive bits and is only
missing the compiler barrier.
That would result in code like:
mov $1, x
lock inc u
lock addl $0, -4(%rsp) # aka smp_mb()
mov y, %r
which is really quite silly.
And as noted in the Changelog, about half the non-value returning
atomics already implied the compiler barrier anyway.
next prev parent reply other threads:[~2019-06-13 18:00 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-13 13:43 [PATCH v2 0/4] atomic: Fixes to smp_mb__{before,after}_atomic() and mips Peter Zijlstra
2019-06-13 13:43 ` [PATCH v2 1/4] mips/atomic: Fix cmpxchg64 barriers Peter Zijlstra
2019-06-13 13:43 ` [PATCH v2 2/4] mips/atomic: Fix loongson_llsc_mb() wreckage Peter Zijlstra
2019-06-13 13:43 ` [PATCH v2 3/4] mips/atomic: Fix smp_mb__{before,after}_atomic() Peter Zijlstra
2019-06-13 13:43 ` [PATCH v2 4/4] x86/atomic: " Peter Zijlstra
2019-06-13 14:02 ` Will Deacon
2019-06-13 14:25 ` [PATCH v2 0/4] atomic: Fixes to smp_mb__{before,after}_atomic() and mips David Howells
2019-06-13 16:58 ` Alan Stern
2019-06-13 18:00 ` Peter Zijlstra [this message]
2019-06-13 16:32 ` Paul Burton
2019-06-13 17:48 ` Peter Zijlstra
2019-08-31 9:00 ` Peter Zijlstra
2019-08-31 10:02 ` Paul Burton
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