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Fri, 14 Jun 2019 09:45:37 -0700 (PDT) Received: from localhost ([64.188.179.243]) by smtp.gmail.com with ESMTPSA id g2sm1831222qkb.80.2019.06.14.09.45.37 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 14 Jun 2019 09:45:37 -0700 (PDT) Date: Fri, 14 Jun 2019 10:45:36 -0600 From: Rob Herring To: Nishanth Menon Cc: Arnd Bergmann , Olof Johansson , Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring , linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tony Lindgren , Russell King , Tero Kristo , Nishanth Menon Subject: Re: [PATCH 1/6] dt-bindings: arm: ti: Add bindings for J721E SoC Message-ID: <20190614164536.GA18039@bogus> References: <20190522161921.20750-1-nm@ti.com> <20190522161921.20750-2-nm@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190522161921.20750-2-nm@ti.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 22 May 2019 11:19:16 -0500, Nishanth Menon wrote: > The J721E SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable lower system costs > of automotive applications such as infotainment, cluster, premium > Audio, Gateway, industrial and a range of broad market applications. > This SoC is designed around reducing the system cost by eliminating > the need of an external system MCU and is targeted towards ASIL-B/C > certification/requirements in addition to allowing complex software > and system use-cases. > > Some highlights of this SoC are: > * Dual Cortex-A72s in a single cluster, three clusters of lockstep > capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), > C7x floating point Vector DSP, Two C66x floating point DSPs. > * 3D GPU PowerVR Rogue 8XE GE8430 > * Vision Processing Accelerator (VPAC) with image signal processor and Depth > and Motion Processing Accelerator (DMPAC) > * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual > PRUs and dual RTUs > * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and > up to two DPI interfaces. > * Integrated Ethernet switch supporting up to a total of 8 external ports in > addition to legacy Ethernet switch of up to 2 ports. > * System MMU (SMMU) Version 3.0 and advanced virtualisation > capabilities. > * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, > 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, > I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL > management. > * Configurable L3 Cache and IO-coherent architecture with high data throughput > capable distributed DMA architecture under NAVSS > * Centralized System Controller for Security, Power, and Resource > Management (DMSC) > > See J721E Technical Reference Manual (SPRUIL1, May 2019) > for further details: http://www.ti.com/lit/pdf/spruil1 > > Signed-off-by: Nishanth Menon > --- > Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ > 1 file changed, 3 insertions(+) > Reviewed-by: Rob Herring