From: Kees Cook <keescook@chromium.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
x86@kernel.org, Peter Zijlstra <peterz@infradead.org>,
Dave Hansen <dave.hansen@intel.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] x86/asm: Pin sensitive CR4 bits
Date: Mon, 17 Jun 2019 21:09:09 -0700 [thread overview]
Message-ID: <201906172050.AA52A49E9@keescook> (raw)
In-Reply-To: <alpine.DEB.2.21.1906170008580.1760@nanos.tec.linutronix.de>
On Mon, Jun 17, 2019 at 12:26:01AM +0200, Thomas Gleixner wrote:
> Nah. The straight forward approach is to do right when the secondary CPU
> comes into life, before it does any cr4 write (except for the code in
> entry_64.S), something like the below.
Okay, will do; thanks! :) I'll respin things and get it tested.
--
Kees Cook
next prev parent reply other threads:[~2019-06-18 4:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-04 23:44 [PATCH v2 0/2] x86/asm: Pin sensitive CR4 and CR0 bits Kees Cook
2019-06-04 23:44 ` [PATCH v2 1/2] x86/asm: Pin sensitive CR4 bits Kees Cook
2019-06-05 14:28 ` Kees Cook
2019-06-14 14:57 ` Thomas Gleixner
2019-06-15 3:19 ` Kees Cook
2019-06-16 22:26 ` Thomas Gleixner
2019-06-18 4:09 ` Kees Cook [this message]
2019-06-04 23:44 ` [PATCH v2 2/2] x86/asm: Pin sensitive CR0 bits Kees Cook
2019-06-14 14:58 ` Thomas Gleixner
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