From: Andi Kleen <ak@linux.intel.com>
To: Jiri Olsa <jolsa@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Kan Liang <kan.liang@intel.com>, Jiri Olsa <jolsa@kernel.org>,
David Carrillo-Cisneros <davidcc@google.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
lkml <linux-kernel@vger.kernel.org>,
Ingo Molnar <mingo@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tom Vaden <tom.vaden@hpe.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Juergen Gross <jgross@suse.com>,
Alok Kataria <akataria@vmware.com>
Subject: Re: [RFC] perf/x86/intel: Disable check_msr for real hw
Date: Mon, 24 Jun 2019 11:38:06 -0700 [thread overview]
Message-ID: <20190624183806.GD31027@tassilo.jf.intel.com> (raw)
In-Reply-To: <20190624180634.GB7292@krava>
> Tom, plz correctme if I'm wrongm but AFAIK because the LBR tracing is
> enabled during the boot the lbr_from/lbr_to registers will fail the
> check_msr 'val_new != val_tmp' check
Ok this should be handleable. It should be enough to check
the ctrl register, if that working likely we don't need
to check the data registers which might be changing.
-Andi
next prev parent reply other threads:[~2019-06-24 18:38 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-14 11:28 [RFC] perf/x86/intel: Disable check_msr for real hw Jiri Olsa
2019-06-14 13:33 ` Peter Zijlstra
2019-06-14 13:45 ` Liang, Kan
2019-06-16 14:13 ` [PATCH] " Jiri Olsa
2019-06-16 20:56 ` Vaden, Tom (HPE Server OS Architecture)
2019-06-17 14:41 ` [tip:perf/core] perf/x86/intel: Disable check_msr for real HW tip-bot for Jiri Olsa
2019-06-21 17:48 ` [RFC] perf/x86/intel: Disable check_msr for real hw Andi Kleen
2019-06-23 22:40 ` Jiri Olsa
2019-06-23 23:44 ` Vaden, Tom (HPE Server OS Architecture)
2019-06-24 8:06 ` Paolo Bonzini
2019-06-24 16:46 ` Andi Kleen
2019-06-24 18:06 ` Jiri Olsa
2019-06-24 18:38 ` Andi Kleen [this message]
2019-06-24 18:49 ` Jiri Olsa
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