From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAA78C0651F for ; Thu, 4 Jul 2019 15:52:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7F1302085A for ; Thu, 4 Jul 2019 15:52:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="cViTZ/CF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727883AbfGDPwZ (ORCPT ); Thu, 4 Jul 2019 11:52:25 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:54300 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727816AbfGDPwZ (ORCPT ); Thu, 4 Jul 2019 11:52:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=svphATbkFOoAAltJuUblfqvoklVJ2Q5WVSnZRTgzpDw=; b=cViTZ/CF344FGf1dtxH/n9m/Ke 59YKl369FU2WptLb8GxVK+48MONjUA7ok4zrdOu2D8uxSz/hy8dVytG0l990Hslraf33EI44o331e JB0i7shiAC7PEC9SmVI4eCccso1cymQV/IuV0WOfu/VyxZOKhQWetiQAXhlypz0rI1XU=; Received: from andrew by vps0.lunn.ch with local (Exim 4.89) (envelope-from ) id 1hj41x-0004lI-Eh; Thu, 04 Jul 2019 17:52:17 +0200 Date: Thu, 4 Jul 2019 17:52:17 +0200 From: Andrew Lunn To: "Voon, Weifeng" Cc: "David S. Miller" , Maxime Coquelin , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Jose Abreu , Giuseppe Cavallaro , Florian Fainelli , Alexandre Torgue , biao huang , "Ong, Boon Leong" , "Kweh, Hock Leong" Subject: Re: [PATCH v1 net-next] net: stmmac: enable clause 45 mdio support Message-ID: <20190704155217.GI18473@lunn.ch> References: <1562147404-4371-1-git-send-email-weifeng.voon@intel.com> <20190703140520.GA18473@lunn.ch> <20190704033038.GA6276@lunn.ch> <20190704135420.GD13859@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Yes, the top 16 bit of the data register only valid when C45 is enable. > It contains the Register address which MDIO c45 frame intended for. I think there is too much passing variables around by reference than by value, to make this code easy to understand. Maybe a better structure would be static int stmmac_mdion_c45_read(struct stmmac_priv *priv, int phyaddr, int phyreg) { unsigned int reg_shift = priv->hw->mii.reg_shift; unsigned int reg_mask = priv->hw->mii.reg_mask; u32 mii_addr_val, mii_data_val; mii_addr_val = MII_GMAC4_C45E | ((phyreg >> MII_DEVADDR_C45_SHIFT) << reg_shift) & reg_mask; mii_data_val = (phyreg & MII_REGADDR_C45_MASK) << MII_GMAC4_REG_ADDR_SHIFT; writel(mii_data_val, priv->ioaddr + priv->hw->mii_data); writel(mii_addr_val, priv->ioaddr + priv->hw->mii_addrress); return (int)readl(priv->ioaddr + mii_data) & MII_DATA_MASK; } static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) { ... if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 100, 10000)) return -EBUSY; if (priv->plat->has_gmac4 && phyreg & MII_ADDR_C45) return stmmac_mdio_c45_read(priv, phyaddr, phyreg); Andrew