From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2664C7618F for ; Mon, 15 Jul 2019 13:47:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 89A182086C for ; Mon, 15 Jul 2019 13:47:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563198454; bh=tAtuICIV1U+7yLjSH6QQHcFpIEFMJc06cGhrtThDr/g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=QR1w/yvK+E78xSM/JTvjoXzD7xnTLFL3KBjWVX+ltmAeY0iqs8cdy7pFbnNsVWFVx iEWXdZriDkWEOuCfQS9YH5KxoinOaQzn+4/NZ+uysFd2tEU1SBRKpUYy69hbkQExO4 AevJ6nm5PvnTmDX6Ygb9j2dL152czfgFWB/SE3RY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731075AbfGONrc (ORCPT ); Mon, 15 Jul 2019 09:47:32 -0400 Received: from mail.kernel.org ([198.145.29.99]:56282 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730996AbfGONr1 (ORCPT ); Mon, 15 Jul 2019 09:47:27 -0400 Received: from sasha-vm.mshome.net (unknown [73.61.17.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 60C56212F5; Mon, 15 Jul 2019 13:47:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563198447; bh=tAtuICIV1U+7yLjSH6QQHcFpIEFMJc06cGhrtThDr/g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DF0bqqqoU3pPMBNa8xbkstplIN5ltQvx5tx6ZJDNqbaVjxaLZywbYhzrx8umCwae/ 1LRH/Ad5sFmxNLTPcmi40fEklJ5QqlTcBeNcAlotWVbu2QrC3UecPD0lQ0f9VzGvfs 6yewJW616x3Cf6Btx+7IW6qdLmwoCDCz4gutYlJc= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Maya Erez , Kalle Valo , Sasha Levin , linux-wireless@vger.kernel.org, wil6210@qti.qualcomm.com, netdev@vger.kernel.org Subject: [PATCH AUTOSEL 5.2 010/249] wil6210: fix missed MISC mbox interrupt Date: Mon, 15 Jul 2019 09:42:55 -0400 Message-Id: <20190715134655.4076-10-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190715134655.4076-1-sashal@kernel.org> References: <20190715134655.4076-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Maya Erez [ Upstream commit 7441be71ba7e07791fd4fa2b07c932dff14ff4d9 ] When MISC interrupt is triggered due to HALP bit, in parallel to mbox events handling by the MISC threaded IRQ, new mbox interrupt can be missed in the following scenario: 1. MISC ICR is read in the IRQ handler 2. Threaded IRQ is completed and all MISC interrupts are unmasked 3. mbox interrupt is set by FW 4. HALP is masked The mbox interrupt in step 3 can be missed due to constant high level of ICM. Masking all MISC IRQs instead of masking only HALP bit in step 4 will guarantee that ICM will drop to 0 and interrupt will be triggered once MISC interrupts will be unmasked. Signed-off-by: Maya Erez Signed-off-by: Kalle Valo Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/wil6210/interrupt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/wil6210/interrupt.c b/drivers/net/wireless/ath/wil6210/interrupt.c index 3f5bd177d55f..e41ba24011d8 100644 --- a/drivers/net/wireless/ath/wil6210/interrupt.c +++ b/drivers/net/wireless/ath/wil6210/interrupt.c @@ -580,7 +580,7 @@ static irqreturn_t wil6210_irq_misc(int irq, void *cookie) /* no need to handle HALP ICRs until next vote */ wil->halp.handle_icr = false; wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n"); - wil6210_mask_halp(wil); + wil6210_mask_irq_misc(wil, true); complete(&wil->halp.comp); } } -- 2.20.1