[PATCH] x86/cpu/intel: Skip CPA cache flush on CPUs with cache self-snooping

[PATCH] x86/cpu/intel: Skip CPA cache flush on CPUs with cache self-snooping

[Uros Bizjak]

CPUs which have self-snooping capability can handle conflicting
memory type across CPUs by snooping its own cache. Commit #fd329f276ecaa
("x86/mtrr: Skip cache flushes on CPUs with cache self-snooping")
avoids cache flushes when MTRR registers are programmed. The Page
Attribute Table (PAT) is a companion feature to the MTRRs, and according
to section 11.12.4 of the Intel 64 and IA 32 Architectures Software
Developer's Manual, if the CPU supports cache self-snooping, it is not
necessary to flush caches when remapping a page that was previously
mapped as a different memory type.

Note that commit #1e03bff360010
("x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata")
cleared cache self-snoop capability for CPUs where conflicting memory types
lead to unpredictable behavior, machine check errors, or hangs.

Signed-off-by: Uros Bizjak <ubizjak@gmail.com>
---
 arch/x86/mm/pageattr.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 6a9a77a403c9..e2704996f9c5 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -1725,10 +1725,11 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
 		goto out;
 
 	/*
-	 * No need to flush, when we did not set any of the caching
-	 * attributes:
+	 * No need to flush when CPU supports self-snoop or
+	 * when we did not set any of the caching attributes:
 	 */
-	cache = !!pgprot2cachemode(mask_set);
+	cache = !static_cpu_has(X86_FEATURE_SELFSNOOP) &&
+		pgprot2cachemode(mask_set);
 
 	/*
 	 * On error; flush everything to be sure.
-- 
2.21.0

Re: [PATCH] x86/cpu/intel: Skip CPA cache flush on CPUs with cache self-snooping

[Andy Lutomirski]

On Mon, Jul 15, 2019 at 7:21 AM Uros Bizjak <ubizjak@gmail.com> wrote:
>
> CPUs which have self-snooping capability can handle conflicting
> memory type across CPUs by snooping its own cache. Commit #fd329f276ecaa
> ("x86/mtrr: Skip cache flushes on CPUs with cache self-snooping")
> avoids cache flushes when MTRR registers are programmed. The Page
> Attribute Table (PAT) is a companion feature to the MTRRs, and according
> to section 11.12.4 of the Intel 64 and IA 32 Architectures Software
> Developer's Manual, if the CPU supports cache self-snooping, it is not
> necessary to flush caches when remapping a page that was previously
> mapped as a different memory type.
>
> Note that commit #1e03bff360010
> ("x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata")
> cleared cache self-snoop capability for CPUs where conflicting memory types
> lead to unpredictable behavior, machine check errors, or hangs.

It looks like this won't affect the SEV code paths, so I'm not
thinking of anything that this will break.  But Dave and Peter are
much, much more familiar with the messes this could cause than I am.

--Andy