Re: [PATCH 08/15] riscv: provide native clint access for M-mode

Palmer Dabbelt
2019-08-27T23:37:20Z

On Mon, 19 Aug 2019 03:16:48 PDT (-0700), Christoph Hellwig wrote:
> On Tue, Aug 13, 2019 at 05:29:58PM +0100, Mark Rutland wrote:
>> > + np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
>>
>> Since the MMIO layout is that of the SiFive clint, the compatible string
>> should be specific to that. e.g. "sifive,clint". That way it will be
>> possible to distinguish it from other implementations.
>>
>> What exactly is the "0" suffix for? Is that a version number?
>>
>> If that's a CPU index, then I don't think that's the right way to encode
>> this unless the programming interface actually differs across CPUs. It
>> would be better to use an explicit phandle to express the affinity.
>
> It isn't a cpu index, I suspect a version number. These show up
> in a lot of the early RISC-V DTs coming from the UCB/SiFive sphere.
> They've now spread everywhere unfortunately.

clint0 would be version 0 of the clint, with is the core-local interrupt
controller in rocket chip. It should be "sifive,clint-1.0.0", not
"riscv,clint0", as it's a SiFive widget. Unfortunately there are a lot of
legacy device trees floating around, but I'm only considering what's been
upstream to be actually part of the spec.

In this case the code should match on a "sifive,clint-1.0.0", and the device
trees should be fixed up to match. We match on "riscv,plic0" for legacy
systems, and I guess it makes sense to do something similar here.