fix radeon and amdgpu for addressing limited root ports

fix radeon and amdgpu for addressing limited root ports

[Christoph Hellwig]

Hi AMD graphics maintainers,

this series fixes a problem in the radeon driver for systems where the
PCIe root port only supports limited (32-bit) addressing as reported
by Atish.  I then also fixed the same issue in amdgpu as the code was
copy and pasted there, and cleaned up the dma mask setting while
touching that area.

[PATCH 1/4] drm/radeon: handle PCIe root ports with addressing limitations

[Christoph Hellwig]

radeon uses a need_dma32 flag to indicate to the drm core that some
allocations need to be done using GFP_DMA32, but it only checks the
device addressing capabilities to make that decision.  Unfortunately
PCIe root ports that have limited addressing exist as well.  Use the
dma_addressing_limited instead to also take those into account.

Reported-by: Atish Patra <Atish.Patra@wdc.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/gpu/drm/radeon/radeon.h        |  1 -
 drivers/gpu/drm/radeon/radeon_device.c | 12 +++++-------
 drivers/gpu/drm/radeon/radeon_ttm.c    |  2 +-
 3 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 32808e50be12..1a0b22526a75 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2387,7 +2387,6 @@ struct radeon_device {
 	struct radeon_wb		wb;
 	struct radeon_dummy_page	dummy_page;
 	bool				shutdown;
-	bool				need_dma32;
 	bool				need_swiotlb;
 	bool				accel_working;
 	bool				fastfb_working; /* IGP feature*/
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index dceb554e5674..b8cc05826667 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1365,27 +1365,25 @@ int radeon_device_init(struct radeon_device *rdev,
 	else
 		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
 
-	/* set DMA mask + need_dma32 flags.
+	/* set DMA mask.
 	 * PCIE - can handle 40-bits.
 	 * IGP - can handle 40-bits
 	 * AGP - generally dma32 is safest
 	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 	 */
-	rdev->need_dma32 = false;
+	dma_bits = 40;
 	if (rdev->flags & RADEON_IS_AGP)
-		rdev->need_dma32 = true;
+		dma_bits = 32;
 	if ((rdev->flags & RADEON_IS_PCI) &&
 	    (rdev->family <= CHIP_RS740))
-		rdev->need_dma32 = true;
+		dma_bits = 32;
 #ifdef CONFIG_PPC64
 	if (rdev->family == CHIP_CEDAR)
-		rdev->need_dma32 = true;
+		dma_bits = 32;
 #endif
 
-	dma_bits = rdev->need_dma32 ? 32 : 40;
 	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 	if (r) {
-		rdev->need_dma32 = true;
 		dma_bits = 32;
 		pr_warn("radeon: No suitable DMA available\n");
 	}
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index fb3696bc616d..116a27b25dc4 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -794,7 +794,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
 	r = ttm_bo_device_init(&rdev->mman.bdev,
 			       &radeon_bo_driver,
 			       rdev->ddev->anon_inode->i_mapping,
-			       rdev->need_dma32);
+			       dma_addressing_limited(&rdev->pdev->dev));
 	if (r) {
 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 		return r;
-- 
2.20.1

Re: [PATCH 1/4] drm/radeon: handle PCIe root ports with addressing limitations

[Koenig, Christian]

Am 15.08.19 um 09:27 schrieb Christoph Hellwig:
> radeon uses a need_dma32 flag to indicate to the drm core that some
> allocations need to be done using GFP_DMA32, but it only checks the
> device addressing capabilities to make that decision.  Unfortunately
> PCIe root ports that have limited addressing exist as well.  Use the
> dma_addressing_limited instead to also take those into account.
>
> Reported-by: Atish Patra <Atish.Patra@wdc.com>
> Signed-off-by: Christoph Hellwig <hch@lst.de>

Looks sane to me. Reviewed-by: Christian König <christian.koenig@amd.com>.

Should we merge this through our normal amdgpu/radeon branches or do you 
want to send this upstream somehow else?

Thanks,
Christian.

> ---
>   drivers/gpu/drm/radeon/radeon.h        |  1 -
>   drivers/gpu/drm/radeon/radeon_device.c | 12 +++++-------
>   drivers/gpu/drm/radeon/radeon_ttm.c    |  2 +-
>   3 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index 32808e50be12..1a0b22526a75 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -2387,7 +2387,6 @@ struct radeon_device {
>   	struct radeon_wb		wb;
>   	struct radeon_dummy_page	dummy_page;
>   	bool				shutdown;
> -	bool				need_dma32;
>   	bool				need_swiotlb;
>   	bool				accel_working;
>   	bool				fastfb_working; /* IGP feature*/
> diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
> index dceb554e5674..b8cc05826667 100644
> --- a/drivers/gpu/drm/radeon/radeon_device.c
> +++ b/drivers/gpu/drm/radeon/radeon_device.c
> @@ -1365,27 +1365,25 @@ int radeon_device_init(struct radeon_device *rdev,
>   	else
>   		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
>   
> -	/* set DMA mask + need_dma32 flags.
> +	/* set DMA mask.
>   	 * PCIE - can handle 40-bits.
>   	 * IGP - can handle 40-bits
>   	 * AGP - generally dma32 is safest
>   	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
>   	 */
> -	rdev->need_dma32 = false;
> +	dma_bits = 40;
>   	if (rdev->flags & RADEON_IS_AGP)
> -		rdev->need_dma32 = true;
> +		dma_bits = 32;
>   	if ((rdev->flags & RADEON_IS_PCI) &&
>   	    (rdev->family <= CHIP_RS740))
> -		rdev->need_dma32 = true;
> +		dma_bits = 32;
>   #ifdef CONFIG_PPC64
>   	if (rdev->family == CHIP_CEDAR)
> -		rdev->need_dma32 = true;
> +		dma_bits = 32;
>   #endif
>   
> -	dma_bits = rdev->need_dma32 ? 32 : 40;
>   	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
>   	if (r) {
> -		rdev->need_dma32 = true;
>   		dma_bits = 32;
>   		pr_warn("radeon: No suitable DMA available\n");
>   	}
> diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
> index fb3696bc616d..116a27b25dc4 100644
> --- a/drivers/gpu/drm/radeon/radeon_ttm.c
> +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
> @@ -794,7 +794,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
>   	r = ttm_bo_device_init(&rdev->mman.bdev,
>   			       &radeon_bo_driver,
>   			       rdev->ddev->anon_inode->i_mapping,
> -			       rdev->need_dma32);
> +			       dma_addressing_limited(&rdev->pdev->dev));
>   	if (r) {
>   		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
>   		return r;

Re: [PATCH 1/4] drm/radeon: handle PCIe root ports with addressing limitations

[Christoph Hellwig]

On Thu, Aug 15, 2019 at 08:34:10AM +0000, Koenig, Christian wrote:
> Looks sane to me. Reviewed-by: Christian König <christian.koenig@amd.com>.
> 
> Should we merge this through our normal amdgpu/radeon branches or do you 
> want to send this upstream somehow else?

This is intended for your trees.

Re: [PATCH 1/4] drm/radeon: handle PCIe root ports with addressing limitations

[Alex Deucher]

On Thu, Aug 15, 2019 at 4:34 AM Koenig, Christian
<Christian.Koenig@amd.com> wrote:
>
> Am 15.08.19 um 09:27 schrieb Christoph Hellwig:
> > radeon uses a need_dma32 flag to indicate to the drm core that some
> > allocations need to be done using GFP_DMA32, but it only checks the
> > device addressing capabilities to make that decision.  Unfortunately
> > PCIe root ports that have limited addressing exist as well.  Use the
> > dma_addressing_limited instead to also take those into account.
> >
> > Reported-by: Atish Patra <Atish.Patra@wdc.com>
> > Signed-off-by: Christoph Hellwig <hch@lst.de>
>
> Looks sane to me. Reviewed-by: Christian König <christian.koenig@amd.com>.

Is this for the full series or just this patch?

Alex

>
> Should we merge this through our normal amdgpu/radeon branches or do you
> want to send this upstream somehow else?
>
> Thanks,
> Christian.
>
> > ---
> >   drivers/gpu/drm/radeon/radeon.h        |  1 -
> >   drivers/gpu/drm/radeon/radeon_device.c | 12 +++++-------
> >   drivers/gpu/drm/radeon/radeon_ttm.c    |  2 +-
> >   3 files changed, 6 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> > index 32808e50be12..1a0b22526a75 100644
> > --- a/drivers/gpu/drm/radeon/radeon.h
> > +++ b/drivers/gpu/drm/radeon/radeon.h
> > @@ -2387,7 +2387,6 @@ struct radeon_device {
> >       struct radeon_wb                wb;
> >       struct radeon_dummy_page        dummy_page;
> >       bool                            shutdown;
> > -     bool                            need_dma32;
> >       bool                            need_swiotlb;
> >       bool                            accel_working;
> >       bool                            fastfb_working; /* IGP feature*/
> > diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
> > index dceb554e5674..b8cc05826667 100644
> > --- a/drivers/gpu/drm/radeon/radeon_device.c
> > +++ b/drivers/gpu/drm/radeon/radeon_device.c
> > @@ -1365,27 +1365,25 @@ int radeon_device_init(struct radeon_device *rdev,
> >       else
> >               rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
> >
> > -     /* set DMA mask + need_dma32 flags.
> > +     /* set DMA mask.
> >        * PCIE - can handle 40-bits.
> >        * IGP - can handle 40-bits
> >        * AGP - generally dma32 is safest
> >        * PCI - dma32 for legacy pci gart, 40 bits on newer asics
> >        */
> > -     rdev->need_dma32 = false;
> > +     dma_bits = 40;
> >       if (rdev->flags & RADEON_IS_AGP)
> > -             rdev->need_dma32 = true;
> > +             dma_bits = 32;
> >       if ((rdev->flags & RADEON_IS_PCI) &&
> >           (rdev->family <= CHIP_RS740))
> > -             rdev->need_dma32 = true;
> > +             dma_bits = 32;
> >   #ifdef CONFIG_PPC64
> >       if (rdev->family == CHIP_CEDAR)
> > -             rdev->need_dma32 = true;
> > +             dma_bits = 32;
> >   #endif
> >
> > -     dma_bits = rdev->need_dma32 ? 32 : 40;
> >       r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
> >       if (r) {
> > -             rdev->need_dma32 = true;
> >               dma_bits = 32;
> >               pr_warn("radeon: No suitable DMA available\n");
> >       }
> > diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
> > index fb3696bc616d..116a27b25dc4 100644
> > --- a/drivers/gpu/drm/radeon/radeon_ttm.c
> > +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
> > @@ -794,7 +794,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
> >       r = ttm_bo_device_init(&rdev->mman.bdev,
> >                              &radeon_bo_driver,
> >                              rdev->ddev->anon_inode->i_mapping,
> > -                            rdev->need_dma32);
> > +                            dma_addressing_limited(&rdev->pdev->dev));
> >       if (r) {
> >               DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
> >               return r;
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 1/4] drm/radeon: handle PCIe root ports with addressing limitations

[Koenig, Christian]

Am 15.08.19 um 16:15 schrieb Alex Deucher:
> On Thu, Aug 15, 2019 at 4:34 AM Koenig, Christian
> <Christian.Koenig@amd.com> wrote:
>> Am 15.08.19 um 09:27 schrieb Christoph Hellwig:
>>> radeon uses a need_dma32 flag to indicate to the drm core that some
>>> allocations need to be done using GFP_DMA32, but it only checks the
>>> device addressing capabilities to make that decision.  Unfortunately
>>> PCIe root ports that have limited addressing exist as well.  Use the
>>> dma_addressing_limited instead to also take those into account.
>>>
>>> Reported-by: Atish Patra <Atish.Patra@wdc.com>
>>> Signed-off-by: Christoph Hellwig <hch@lst.de>
>> Looks sane to me. Reviewed-by: Christian König <christian.koenig@amd.com>.
> Is this for the full series or just this patch?

For the full series, sorry for not being clear on this.

Christian.

>
> Alex
>
>> Should we merge this through our normal amdgpu/radeon branches or do you
>> want to send this upstream somehow else?
>>
>> Thanks,
>> Christian.
>>
>>> ---
>>>    drivers/gpu/drm/radeon/radeon.h        |  1 -
>>>    drivers/gpu/drm/radeon/radeon_device.c | 12 +++++-------
>>>    drivers/gpu/drm/radeon/radeon_ttm.c    |  2 +-
>>>    3 files changed, 6 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
>>> index 32808e50be12..1a0b22526a75 100644
>>> --- a/drivers/gpu/drm/radeon/radeon.h
>>> +++ b/drivers/gpu/drm/radeon/radeon.h
>>> @@ -2387,7 +2387,6 @@ struct radeon_device {
>>>        struct radeon_wb                wb;
>>>        struct radeon_dummy_page        dummy_page;
>>>        bool                            shutdown;
>>> -     bool                            need_dma32;
>>>        bool                            need_swiotlb;
>>>        bool                            accel_working;
>>>        bool                            fastfb_working; /* IGP feature*/
>>> diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
>>> index dceb554e5674..b8cc05826667 100644
>>> --- a/drivers/gpu/drm/radeon/radeon_device.c
>>> +++ b/drivers/gpu/drm/radeon/radeon_device.c
>>> @@ -1365,27 +1365,25 @@ int radeon_device_init(struct radeon_device *rdev,
>>>        else
>>>                rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
>>>
>>> -     /* set DMA mask + need_dma32 flags.
>>> +     /* set DMA mask.
>>>         * PCIE - can handle 40-bits.
>>>         * IGP - can handle 40-bits
>>>         * AGP - generally dma32 is safest
>>>         * PCI - dma32 for legacy pci gart, 40 bits on newer asics
>>>         */
>>> -     rdev->need_dma32 = false;
>>> +     dma_bits = 40;
>>>        if (rdev->flags & RADEON_IS_AGP)
>>> -             rdev->need_dma32 = true;
>>> +             dma_bits = 32;
>>>        if ((rdev->flags & RADEON_IS_PCI) &&
>>>            (rdev->family <= CHIP_RS740))
>>> -             rdev->need_dma32 = true;
>>> +             dma_bits = 32;
>>>    #ifdef CONFIG_PPC64
>>>        if (rdev->family == CHIP_CEDAR)
>>> -             rdev->need_dma32 = true;
>>> +             dma_bits = 32;
>>>    #endif
>>>
>>> -     dma_bits = rdev->need_dma32 ? 32 : 40;
>>>        r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
>>>        if (r) {
>>> -             rdev->need_dma32 = true;
>>>                dma_bits = 32;
>>>                pr_warn("radeon: No suitable DMA available\n");
>>>        }
>>> diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
>>> index fb3696bc616d..116a27b25dc4 100644
>>> --- a/drivers/gpu/drm/radeon/radeon_ttm.c
>>> +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
>>> @@ -794,7 +794,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
>>>        r = ttm_bo_device_init(&rdev->mman.bdev,
>>>                               &radeon_bo_driver,
>>>                               rdev->ddev->anon_inode->i_mapping,
>>> -                            rdev->need_dma32);
>>> +                            dma_addressing_limited(&rdev->pdev->dev));
>>>        if (r) {
>>>                DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
>>>                return r;
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 2/4] drm/amdgpu: handle PCIe root ports with addressing limitations

[Christoph Hellwig]

amdgpu uses a need_dma32 flag to indicate to the drm core that some
allocations need to be done using GFP_DMA32, but it only checks the
device addressing capabilities to make that decision.  Unfortunately
PCIe root ports that have limited addressing exist as well.  Use the
dma_addressing_limited instead to also take those into account.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e51b48ac48eb..91f128b43b6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1728,7 +1728,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 	r = ttm_bo_device_init(&adev->mman.bdev,
 			       &amdgpu_bo_driver,
 			       adev->ddev->anon_inode->i_mapping,
-			       adev->need_dma32);
+			       dma_addressing_limited(adev->dev));
 	if (r) {
 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 		return r;
-- 
2.20.1

[PATCH 3/4] drm/radeon: simplify and cleanup setting the dma mask

[Christoph Hellwig]

Use dma_set_mask_and_coherent to set both masks in one go, and remove
the no longer required fallback, as the kernel now always accepts
larger than required DMA masks.  Fail the driver probe if we can't
set the DMA mask, as that means the system can only support a larger
mask.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/gpu/drm/radeon/radeon_device.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index b8cc05826667..88eb7cb522bb 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1382,15 +1382,10 @@ int radeon_device_init(struct radeon_device *rdev,
 		dma_bits = 32;
 #endif
 
-	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
+	r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
 	if (r) {
-		dma_bits = 32;
 		pr_warn("radeon: No suitable DMA available\n");
-	}
-	r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
-	if (r) {
-		pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
-		pr_warn("radeon: No coherent DMA available\n");
+		return r;
 	}
 	rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
 
-- 
2.20.1

[PATCH 4/4] drm/amdgpu: simplify and cleanup setting the dma mask

[Christoph Hellwig]

Use dma_set_mask_and_coherent to set both masks in one go, and remove
the no longer required fallback, as the kernel now always accepts
larger than required DMA masks.  Fail the driver probe if we can't
set the DMA mask, as that means the system can only support a larger
mask.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 21 ++-------------------
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 15 +++------------
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 20 +++-----------------
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 20 +++-----------------
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 20 +++-----------------
 6 files changed, 14 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8199d201b43a..ab562c27bb44 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -758,7 +758,6 @@ struct amdgpu_device {
 	int				usec_timeout;
 	const struct amdgpu_asic_funcs	*asic_funcs;
 	bool				shutdown;
-	bool				need_dma32;
 	bool				need_swiotlb;
 	bool				accel_working;
 	struct notifier_block		acpi_nb;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 5eeb72fcc123..05c8872eb8d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -590,7 +590,6 @@ static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
 static int gmc_v10_0_sw_init(void *handle)
 {
 	int r;
-	int dma_bits;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	gfxhub_v2_0_init(adev);
@@ -637,26 +636,10 @@ static int gmc_v10_0_sw_init(void *handle)
 	else
 		adev->gmc.stolen_size = 9 * 1024 *1024;
 
-	/*
-	 * Set DMA mask + need_dma32 flags.
-	 * PCIE - can handle 44-bits.
-	 * IGP - can handle 44-bits
-	 * PCI - dma32 for legacy pci gart, 44 bits on navi10
-	 */
-	adev->need_dma32 = false;
-	dma_bits = adev->need_dma32 ? 32 : 44;
-
-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 	if (r) {
-		adev->need_dma32 = true;
-		dma_bits = 32;
 		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
-	}
-
-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
-	if (r) {
-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
-		printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
+		return r;
 	}
 
 	r = gmc_v10_0_mc_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index ca8dbe91cc8b..14073b506afe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -839,7 +839,6 @@ static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
 static int gmc_v6_0_sw_init(void *handle)
 {
 	int r;
-	int dma_bits;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	if (adev->flags & AMD_IS_APU) {
@@ -862,20 +861,12 @@ static int gmc_v6_0_sw_init(void *handle)
 
 	adev->gmc.mc_mask = 0xffffffffffULL;
 
-	adev->need_dma32 = false;
-	dma_bits = adev->need_dma32 ? 32 : 40;
-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 	if (r) {
-		adev->need_dma32 = true;
-		dma_bits = 32;
 		dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
+		return r;
 	}
-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
-	if (r) {
-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
-		dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
-	}
-	adev->need_swiotlb = drm_need_swiotlb(dma_bits);
+	adev->need_swiotlb = drm_need_swiotlb(44);
 
 	r = gmc_v6_0_init_microcode(adev);
 	if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 57f80065d57a..ca32915fbecb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -959,7 +959,6 @@ static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
 static int gmc_v7_0_sw_init(void *handle)
 {
 	int r;
-	int dma_bits;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	if (adev->flags & AMD_IS_APU) {
@@ -990,25 +989,12 @@ static int gmc_v7_0_sw_init(void *handle)
 	 */
 	adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 
-	/* set DMA mask + need_dma32 flags.
-	 * PCIE - can handle 40-bits.
-	 * IGP - can handle 40-bits
-	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
-	 */
-	adev->need_dma32 = false;
-	dma_bits = adev->need_dma32 ? 32 : 40;
-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
 	if (r) {
-		adev->need_dma32 = true;
-		dma_bits = 32;
 		pr_warn("amdgpu: No suitable DMA available\n");
+		return r;
 	}
-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
-	if (r) {
-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
-		pr_warn("amdgpu: No coherent DMA available\n");
-	}
-	adev->need_swiotlb = drm_need_swiotlb(dma_bits);
+	adev->need_swiotlb = drm_need_swiotlb(40);
 
 	r = gmc_v7_0_init_microcode(adev);
 	if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9238280d1ff7..909a8764703e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1079,7 +1079,6 @@ static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
 static int gmc_v8_0_sw_init(void *handle)
 {
 	int r;
-	int dma_bits;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	if (adev->flags & AMD_IS_APU) {
@@ -1116,25 +1115,12 @@ static int gmc_v8_0_sw_init(void *handle)
 	 */
 	adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 
-	/* set DMA mask + need_dma32 flags.
-	 * PCIE - can handle 40-bits.
-	 * IGP - can handle 40-bits
-	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
-	 */
-	adev->need_dma32 = false;
-	dma_bits = adev->need_dma32 ? 32 : 40;
-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
 	if (r) {
-		adev->need_dma32 = true;
-		dma_bits = 32;
 		pr_warn("amdgpu: No suitable DMA available\n");
+		return r;
 	}
-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
-	if (r) {
-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
-		pr_warn("amdgpu: No coherent DMA available\n");
-	}
-	adev->need_swiotlb = drm_need_swiotlb(dma_bits);
+	adev->need_swiotlb = drm_need_swiotlb(40);
 
 	r = gmc_v8_0_init_microcode(adev);
 	if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 73f3b79ab131..38b91a407e6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -968,7 +968,6 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
 static int gmc_v9_0_sw_init(void *handle)
 {
 	int r;
-	int dma_bits;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	gfxhub_v1_0_init(adev);
@@ -1030,25 +1029,12 @@ static int gmc_v9_0_sw_init(void *handle)
 	 */
 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 
-	/* set DMA mask + need_dma32 flags.
-	 * PCIE - can handle 44-bits.
-	 * IGP - can handle 44-bits
-	 * PCI - dma32 for legacy pci gart, 44 bits on vega10
-	 */
-	adev->need_dma32 = false;
-	dma_bits = adev->need_dma32 ? 32 : 44;
-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 	if (r) {
-		adev->need_dma32 = true;
-		dma_bits = 32;
 		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
+		return r;
 	}
-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
-	if (r) {
-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
-		printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
-	}
-	adev->need_swiotlb = drm_need_swiotlb(dma_bits);
+	adev->need_swiotlb = drm_need_swiotlb(44);
 
 	if (adev->gmc.xgmi.supported) {
 		r = gfxhub_v1_1_get_xgmi_info(adev);
-- 
2.20.1