From: Borislav Petkov <bp@alien8.de>
To: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/7] AMD64 EDAC fixes
Date: Fri, 16 Aug 2019 08:47:44 +0200 [thread overview]
Message-ID: <20190816064744.GE18980@zn.tnic> (raw)
In-Reply-To: <SN6PR12MB263968E448E4CCD4C6856288F8AC0@SN6PR12MB2639.namprd12.prod.outlook.com>
On Thu, Aug 15, 2019 at 08:08:39PM +0000, Ghannam, Yazen wrote:
> Yes, I agree. I was planning to do a fix in a separate set. Is that
> okay? Or should I add it here?
If you have it, send it on, sure.
Thx.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
prev parent reply other threads:[~2019-08-16 6:46 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-09 21:56 [PATCH v2 0/7] AMD64 EDAC fixes Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 1/7] EDAC/amd64: Support more than two controllers for chip selects handling Ghannam, Yazen
2019-07-10 16:54 ` Phillips, Kim
2019-08-02 6:49 ` Borislav Petkov
2019-08-19 19:55 ` Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 3/7] EDAC/amd64: Initialize DIMM info for systems with more than two channels Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 2/7] EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP Ghannam, Yazen
2019-08-02 7:42 ` Borislav Petkov
2019-08-19 20:19 ` Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 4/7] EDAC/amd64: Find Chip Select memory size using Address Mask Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 5/7] EDAC/amd64: Decode syndrome before translating address Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 6/7] EDAC/amd64: Cache secondary Chip Select registers Ghannam, Yazen
2019-07-09 21:56 ` [PATCH v2 7/7] EDAC/amd64: Support Asymmetric Dual-Rank DIMMs Ghannam, Yazen
2019-08-02 14:46 ` [PATCH v2 0/7] AMD64 EDAC fixes Borislav Petkov
2019-08-15 20:08 ` Ghannam, Yazen
2019-08-16 6:47 ` Borislav Petkov [this message]
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