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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id m7sm8447750otm.5.2019.08.21.13.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2019 13:56:50 -0700 (PDT) Date: Wed, 21 Aug 2019 15:56:50 -0500 From: Rob Herring To: Tomer Maimon Cc: broonie@kernel.org, mark.rutland@arm.com, vigneshr@ti.com, bbrezillon@kernel.org, avifishman70@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] dt-binding: spi: add NPCM FIU controller Message-ID: <20190821205650.GA14884@bogus> References: <20190808131448.349161-1-tmaimon77@gmail.com> <20190808131448.349161-2-tmaimon77@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190808131448.349161-2-tmaimon77@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 08, 2019 at 04:14:47PM +0300, Tomer Maimon wrote: > Added device tree binding documentation for Nuvoton BMC > NPCM Flash Interface Unit(FIU) SPI master controller > using SPI-MEM interface. > > Signed-off-by: Tomer Maimon > --- > .../bindings/spi/nuvoton,npcm-fiu.txt | 47 +++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt > > diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt > new file mode 100644 > index 000000000000..ab37aae91d19 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt > @@ -0,0 +1,47 @@ > +* Nuvoton FLASH Interface Unit (FIU) SPI Controller > + > +NPCM FIU supports single, dual and quad communication interface. > + > +The NPCM7XX supports three FIU modules, > +FIU0 and FIUx supports two chip selects, > +FIU3 support four chip select. > + > +Required properties: > + - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC > + - #address-cells : should be 1. > + - #size-cells : should be 0. > + - reg : the first contains the register location and length, > + the second contains the memory mapping address and length > + - reg-names: Should contain the reg names "control" and "memory" > + - clocks : phandle of FIU reference clock. > + > +Required properties in case the pins can be muxed: > + - pinctrl-names : a pinctrl state named "default" must be defined. > + - pinctrl-0 : phandle referencing pin configuration of the device. > + > +Optional property: > + - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. Is this something standard? If not, add a vendor prefix. > + > +Aliases: > +- All the FIU controller nodes should be represented in the aliases node using > + the following format 'fiu{n}' where n is a unique number for the alias. > + In the NPCM7XX BMC: > + fiu0 represent fiu 0 controller > + fiu1 represent fiu 3 controller > + fiu2 represent fiu x controller > + > +Example: > +fiu3: fiu@c00000000 { spi@... > + compatible = "nuvoton,npcm750-fiu"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; > + reg-names = "control", "memory"; > + clocks = <&clk NPCM7XX_CLK_AHB>; > + pinctrl-names = "default"; > + pinctrl-0 = <&spi3_pins>; > + spi-nor@0 { > + ... > + }; > +}; > + > -- > 2.18.0 >